N. Engelhardt
81f87ce6ed
Revert "Add groups to command reference"
2025-07-23 14:41:49 +00:00
Robert O'Callahan
f25f8fe7c4
In the Verilog backend, only sort modules that we're going to emit.
...
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.
We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
2025-07-21 05:32:31 +00:00
Krystine Sherwin
d62a110dc8
register.h: Add internal_flag to Pass
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Update experimental pass warnings to use a shared function. Reduces repetition, and also allows all of the warning flags to be combined (which at present is just experimental and the new internal).
Update `test_*` passes to call `internal()` in their constructors.
2025-07-21 10:35:19 +12:00
George Rennie
381381c997
write_firrtl: clear used names cache each pass
2025-07-15 14:14:07 +01:00
Emil J. Tywoniak
2b659626a3
rename: add -unescape
2025-06-24 12:33:33 +02:00
Emil J
c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs
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aiger: fix -map and -vmap
2025-06-02 15:07:19 +02:00
N. Engelhardt
1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering
2025-06-02 13:06:36 +00:00
Krystine Sherwin
aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO
2025-05-31 09:55:00 +12:00
Krystine Sherwin
0072a267cc
write_aiger: Add no-sort option
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Prevents sorting input/output bits so that they remain in the same order they were read in.
2025-05-29 16:20:16 +12:00
gatecat
45a6940f40
cxxrtl: Add debug items for state with private names
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Signed-off-by: gatecat <gatecat@ds0.me>
2025-05-26 16:58:13 +02:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
Gus Smith
d8b27d41c0
Bugfix
2025-05-21 21:31:07 -07:00
Gus Smith
8ec9de00ec
Use ir.inputs()/ir.outputs()
2025-05-20 17:45:23 -07:00
Gus Smith
af51097af7
Convert to 'assoc list helpers'
2025-05-18 18:01:43 -07:00
Gus Smith
a55dc80175
Rename parameter
2025-05-17 16:04:17 -07:00
Gus Smith
c1111f125c
Add output helper as well
2025-05-17 15:19:09 -07:00
Gus Smith
1fdfba2a1a
Add helper for accessing by base name
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The existing access function isn't useful if we don't have access to the original
names of the input/output/state signals. There may be a better way to do this, but
it might require restructuring the SmtrStruct.
2025-05-17 15:17:29 -07:00
Gus Smith
10b8fdddb4
Rename argument
2025-05-17 14:39:11 -07:00
Gus Smith
7b4c9c5dcd
Add optional keyword-based constructor
2025-05-17 14:12:09 -07:00
Gus Smith
fd5918c811
get_field_names for structs
2025-05-17 14:10:23 -07:00
Emil J. Tywoniak
f73c6a9c9a
write_verilog: don't dump single_bit_vector attribute
2025-05-12 13:36:25 +02:00
Emil J. Tywoniak
5e72464a15
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
Emil J. Tywoniak
2522bcd492
aiger: fix -map and -vmap
2025-05-09 14:21:10 +02:00
Emil J. Tywoniak
90a2c92370
driver: allow --no-version still write things like Generated by Yosys
2025-05-07 11:34:23 +02:00
Emil J. Tywoniak
d7affb8821
driver: add --no-version to suppress writing Yosys version in command outputs
2025-05-05 13:12:08 +02:00
sdjasj
da1ac9ae47
cxxrtl: fix missing sign extension before shift operation for signed values
2025-05-03 09:38:16 +00:00
Catherine
3d1f2161dc
cxxrtl: strip $paramod from module name in scope info.
2025-04-26 14:51:21 +01:00
sdjasj
b693947834
fix udivmod crashes when operand value exceeds logical width
2025-04-24 14:33:52 +01:00
David Sawatzke
04098933c7
cxxrtl: Add internal cell "bwmux"
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Mirrors the implementation for the smt2 backend
Co-authored-by: Martin Povišer <povik@cutebit.org>
2025-04-16 13:58:08 +01:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
KrystalDelusion
9fa1f0e70c
Merge pull request #4567 from kivikakk/cxxrtl-escape-trailing
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cxxrtl: use octal encoding of non-printables.
2025-03-14 16:52:07 +13:00
Krystine Sherwin
46a311acb2
firrtl: Drop full_selection check
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Change `top` pointer default to `nullptr` to avoid issues with `Design->top_module()` only operating on the current selection.
Calls to other passes (`bmuxmap` etc) will only operate on the current selection, and may cause problems when those cells are unprocessed, but this is consistent with the other backends that only operate on the full designs and will hopefully be fixed in another PR soon :)
2025-03-14 14:08:56 +13:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
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Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
KrystalDelusion
65748b8387
Merge pull request #4898 from Anhijkt/fix-xaiger-segfault
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write_xaiger: Detect and error on combinatorial loops
2025-03-13 10:49:48 +13:00
N. Engelhardt
c74df780b7
Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial
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Docs: More on FunctionalIR
2025-03-10 15:05:55 +00:00
Anhijkt
a8052f653a
write_xaiger: Detect and error on combinatorial loops
2025-02-14 01:21:39 +02:00
Krystine Sherwin
fa2d45a922
smtr: Refactor write back into _eval and _initial
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Easier for comparisons, and the structure still works. (I don't remember why I moved away from it in the first place.)
2025-02-07 13:58:09 +13:00
Robin Ole Heinemann
0ab13924a5
write_verilog: log_abort on unhandled $check flavor
2025-01-30 14:18:02 +00:00
Robin Ole Heinemann
2f11dc87c9
write_verilog: emit $check cell names as labels
2025-01-30 14:18:02 +00:00
Catherine
3076803c9e
write_json: missing \n in help text.
2025-01-23 05:17:52 +00:00
N. Engelhardt
77b28442a5
emit $scopeinfo cells by default
2025-01-08 14:47:46 +01:00
N. Engelhardt
dab7905cbe
write_json: add option to include $scopeinfo cells
2025-01-08 13:33:56 +01:00
Krystine Sherwin
7698dfba5e
smtr: Fix help text
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Can't take both [selection] and [filename] optional arguments.
2025-01-06 14:31:50 +13:00
Catherine
1ef4c7f565
yosys-smtbmc: add cvc5 to help text.
2024-12-25 04:59:02 +00:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Martin Povišer
86fad8f6f5
Merge pull request #4803 from povik/write_verilog-buf
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write_verilog: Use assign for `$buf`
2024-12-10 20:10:58 +01:00
Martin Povišer
559209c856
abc_new: Fix PI confusion in whitebox model export
2024-12-10 14:27:29 +01:00
