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Revert "Refactor full_selection"

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Miodrag Milanović 2025-04-07 12:11:55 +02:00 • committed by GitHub
parent 98d4355b82
commit d49364d96f
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38 changed files with 270 additions and 707 deletions
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5
backends/firrtl/firrtl.cc
View file

@ -1215,6 +1215,9 @@ struct FirrtlBackend : public Backend {
}
extra_args(f, filename, args, argidx);
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
log_header(design, "Executing FIRRTL backend.\n");
log_push();
@ -1227,7 +1230,7 @@ struct FirrtlBackend : public Backend {
autoid_counter = 0;
// Get the top module, or a reasonable facsimile - we need something for the circuit name.
Module *top = nullptr;
Module *top = design->top_module();
Module *last = nullptr;
// Generate module and wire names.
for (auto module : design->modules()) {

4
backends/rtlil/rtlil_backend.cc
View file

@ -304,8 +304,8 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::
void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
{
bool print_header = flag_m || module->is_selected_whole();
bool print_body = !flag_n || !module->is_selected_whole();
bool print_header = flag_m || design->selected_whole_module(module->name);
bool print_body = !flag_n || !design->selected_whole_module(module->name);
if (print_header)
{