mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-11 17:54:44 +00:00
Code Activity

driver: add --no-version to suppress writing Yosys version in command outputs

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-05 13:12:08 +02:00
parent f60bbe64ac
commit d7affb8821
14 changed files with 31 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/aiger/aiger.cc
View file

@ -662,8 +662,8 @@ struct AigerWriter
f << std::endl;
}
}
f << stringf("c\nGenerated by %s\n", yosys_version_str);
if (yosys_write_versions)
f << stringf("c\nGenerated by %s\n", yosys_version_str);
}
void write_map(std::ostream &f, bool verbose_map, bool no_startoffset)

3
backends/aiger/xaiger.cc
View file

@ -671,7 +671,8 @@ struct XAigerWriter
//f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
//f.write(buffer_str.data(), buffer_str.size());
f << stringf("Generated by %s\n", yosys_version_str);
if (yosys_write_versions)
f << stringf("Generated by %s\n", yosys_version_str);
design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());

3
backends/blif/blif.cc
View file

@ -649,7 +649,8 @@ struct BlifBackend : public Backend {
if (module->get_bool_attribute(ID::top))
top_module_name = module->name.str();
*f << stringf("# Generated by %s\n", yosys_version_str);
if (yosys_write_versions)
*f << stringf("# Generated by %s\n", yosys_version_str);
std::vector<RTLIL::Module*> mod_list;

4
backends/edif/edif.cc
View file

@ -231,7 +231,9 @@ struct EdifBackend : public Backend {
*f << stringf(" (edifVersion 2 0 0)\n");
*f << stringf(" (edifLevel 0)\n");
*f << stringf(" (keywordMap (keywordLevel 0))\n");
*f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
if (yosys_write_versions)
*f << stringf(" (comment \"Generated by %s\")\n", yosys_version_str);
*f << stringf(" (external LIB\n");
*f << stringf(" (edifLevel 0)\n");

3
backends/json/json.cc
View file

@ -291,7 +291,8 @@ struct JsonWriter
design->sort();
f << stringf("{\n");
f << stringf(" \"creator\": %s,\n", get_string(yosys_version_str).c_str());
if (yosys_write_versions)
f << stringf(" \"creator\": %s,\n", get_string(yosys_version_str).c_str());
f << stringf(" \"modules\": {\n");
vector<Module*> modules = use_selection ? design->selected_modules() : design->modules();
bool first_module = true;

4
backends/rtlil/rtlil_backend.cc
View file

@ -459,7 +459,9 @@ struct RTLILBackend : public Backend {
design->sort();
log("Output filename: %s\n", filename.c_str());
*f << stringf("# Generated by %s\n", yosys_version_str);
if (yosys_write_versions)
*f << stringf("# Generated by %s\n", yosys_version_str);
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
}
} RTLILBackend;

1
backends/smt2/smtio.py
View file

@ -1289,6 +1289,7 @@ class MkVcd:
assert t >= self.t
if t != self.t:
if self.t == -1:
# TODO if (yosys_write_versions) equivalent?
print("$version Generated by Yosys-SMTBMC $end", file=self.f)
print("$timescale 1ns $end", file=self.f)
print("$var integer 32 t smt_step $end", file=self.f)

4
backends/verilog/verilog_backend.cc
View file

@ -2596,7 +2596,9 @@ struct VerilogBackend : public Backend {
design->sort();
*f << stringf("/* Generated by %s */\n", yosys_version_str);
if (yosys_write_versions)
*f << stringf("/* Generated by %s */\n", yosys_version_str);
for (auto module : design->modules()) {
if (module->get_blackbox_attribute() != blackboxes)
continue;