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Merge pull request #5150 from YosysHQ/krys/aiger_ordering
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commit
1c742441db
1 changed files with 49 additions and 25 deletions
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@ -132,7 +132,7 @@ struct AigerWriter
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return a;
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}
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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AigerWriter(Module *module, bool no_sort, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -152,6 +152,37 @@ struct AigerWriter
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if (wire->port_input)
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sigmap.add(wire);
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// handle ports
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// provided the input_bits and output_bits don't get sorted they
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// will be returned in reverse order, so add them in reverse to
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// match
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for (auto riter = module->ports.rbegin(); riter != module->ports.rend(); ++riter) {
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auto *wire = module->wire(*riter);
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire == nullptr) {
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if (wire->port_output) {
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aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
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output_bits.insert(wirebit);
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}
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continue;
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}
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if (wire->port_input)
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input_bits.insert(bit);
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if (wire->port_output) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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}
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// handle wires
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for (auto wire : module->wires())
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{
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if (wire->attributes.count(ID::init)) {
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@ -167,25 +198,13 @@ struct AigerWriter
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire == nullptr) {
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if (wire->port_output) {
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aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
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output_bits.insert(wirebit);
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}
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if (bit.wire == nullptr)
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continue;
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if (wire->port_input || wire->port_output)
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continue;
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}
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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if (wire->port_input)
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input_bits.insert(bit);
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if (wire->port_output) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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if (wire->width == 1) {
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@ -200,12 +219,6 @@ struct AigerWriter
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}
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}
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for (auto bit : input_bits)
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undriven_bits.erase(bit);
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for (auto bit : output_bits)
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unused_bits.erase(bit);
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for (auto cell : module->cells())
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{
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if (cell->type == ID($_NOT_))
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@ -343,8 +356,11 @@ struct AigerWriter
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}
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init_map.sort();
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input_bits.sort();
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output_bits.sort();
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// we are relying here on unsorted pools iterating last-in-first-out
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if (!no_sort) {
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input_bits.sort();
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output_bits.sort();
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}
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not_map.sort();
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ff_map.sort();
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and_map.sort();
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@ -901,6 +917,9 @@ struct AigerBackend : public Backend {
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log(" -symbols\n");
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log(" include a symbol table in the generated AIGER file\n");
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log("\n");
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log(" -no-sort\n");
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log(" don't sort input/output ports\n");
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log("\n");
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log(" -map <filename>\n");
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log(" write an extra file with port and latch symbols\n");
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log("\n");
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@ -925,6 +944,7 @@ struct AigerBackend : public Backend {
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bool zinit_mode = false;
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bool miter_mode = false;
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bool symbols_mode = false;
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bool no_sort = false;
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bool verbose_map = false;
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bool imode = false;
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bool omode = false;
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@ -955,6 +975,10 @@ struct AigerBackend : public Backend {
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symbols_mode = true;
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continue;
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}
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if (args[argidx] == "-no-sort") {
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no_sort = true;
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continue;
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}
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if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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@ -1008,7 +1032,7 @@ struct AigerBackend : public Backend {
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if (!top_module->memories.empty())
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log_error("Found unmapped memories in module %s: unmapped memories are not supported in AIGER backend!\n", log_id(top_module));
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AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
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AigerWriter writer(top_module, no_sort, zinit_mode, imode, omode, bmode, lmode);
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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if (!map_filename.empty()) {
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