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rename: add -unescape
This commit is contained in:
Emil J. Tywoniak
parent
513f0f16dd
commit
2b659626a3
4 changed files with 215 additions and 46 deletions
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@ -28,12 +28,71 @@
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#include "kernel/ff.h"
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#include "kernel/mem.h"
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#include "kernel/fmt.h"
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#include "backends/verilog/verilog_backend.h"
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#include <string>
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#include <sstream>
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#include <set>
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#include <map>
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USING_YOSYS_NAMESPACE
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using namespace VERILOG_BACKEND;
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const pool<string> VERILOG_BACKEND::verilog_keywords() {
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static const pool<string> res = {
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// IEEE 1800-2017 Annex B
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"accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before",
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"begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle",
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"checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint",
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"cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker",
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"endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage",
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"endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually",
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"expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function",
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"generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies",
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"import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface",
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"intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint",
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"macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor",
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"noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive",
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"priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent",
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"pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat",
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"restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until",
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"s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify",
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"specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on",
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"sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1",
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"tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with",
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"untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while",
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"wildcard", "wire", "with", "within", "wor", "xnor", "xor",
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};
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return res;
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}
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bool VERILOG_BACKEND::char_is_verilog_escaped(char c) {
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if ('0' <= c && c <= '9')
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return false;
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if ('a' <= c && c <= 'z')
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return false;
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if ('A' <= c && c <= 'Z')
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return false;
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if (c == '_')
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return false;
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return true;
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}
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bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) {
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if ('0' <= str[0] && str[0] <= '9')
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return true;
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for (int i = 0; str[i]; i++)
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if (char_is_verilog_escaped(str[i]))
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return true;
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if (verilog_keywords().count(str))
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return true;
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return false;
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}
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PRIVATE_NAMESPACE_BEGIN
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase;
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@ -105,7 +164,6 @@ std::string next_auto_id()
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std::string id(RTLIL::IdString internal_id, bool may_rename = true)
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{
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const char *str = internal_id.c_str();
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bool do_escape = false;
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if (may_rename && auto_name_map.count(internal_id) != 0)
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return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_map[internal_id]);
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@ -113,51 +171,7 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true)
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if (*str == '\\')
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str++;
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if ('0' <= *str && *str <= '9')
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do_escape = true;
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for (int i = 0; str[i]; i++)
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{
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if ('0' <= str[i] && str[i] <= '9')
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continue;
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if ('a' <= str[i] && str[i] <= 'z')
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continue;
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if ('A' <= str[i] && str[i] <= 'Z')
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continue;
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if (str[i] == '_')
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continue;
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do_escape = true;
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break;
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}
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static const pool<string> keywords = {
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// IEEE 1800-2017 Annex B
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"accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before",
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"begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle",
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"checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint",
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"cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker",
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"endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage",
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"endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually",
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"expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function",
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"generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies",
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"import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface",
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"intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint",
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"macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor",
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"noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive",
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"priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent",
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"pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat",
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"restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until",
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"s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify",
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"specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on",
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"sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1",
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"tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with",
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"untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while",
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"wildcard", "wire", "with", "within", "wor", "xnor", "xor",
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};
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if (keywords.count(str))
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do_escape = true;
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if (do_escape)
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if (id_is_verilog_escaped(str))
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return "\\" + std::string(str) + " ";
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return std::string(str);
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}
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39
backends/verilog/verilog_backend.h
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39
backends/verilog/verilog_backend.h
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@ -0,0 +1,39 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* A simple and straightforward Verilog backend.
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*
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*/
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#ifndef VERILOG_BACKEND_H
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#define VERILOG_BACKEND_H
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#include <string>
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_BACKEND {
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const pool<string> verilog_keywords();
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bool char_is_verilog_escaped(char c);
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bool id_is_verilog_escaped(const std::string &str);
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}; /* namespace VERILOG_BACKEND */
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YOSYS_NAMESPACE_END
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#endif /* VERILOG_BACKEND_H */
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