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yosys/backends
Robert O'Callahan f25f8fe7c4 In the Verilog backend, only sort modules that we're going to emit.
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.

We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
2025-07-21 05:32:31 +00:00
..
aiger Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs 2025-06-02 15:07:19 +02:00
aiger2 abc_new: Fix PI confusion in whitebox model export 2024-12-10 14:27:29 +01:00
blif driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
btor driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
cxxrtl cxxrtl: Add debug items for state with private names 2025-05-26 16:58:13 +02:00
edif driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
firrtl write_firrtl: clear used names cache each pass 2025-07-15 14:14:07 +01:00
functional smtr: Refactor write back into _eval and _initial 2025-02-07 13:58:09 +13:00
intersynth rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
jny driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
json driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
rtlil driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
simplec rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
smt2 driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
smv driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
spice driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
table Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
verilog In the Verilog backend, only sort modules that we're going to emit. 2025-07-21 05:32:31 +00:00