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Code Activity
16037 commits 122 branches 59 tags 72 MiB
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2021 commits

Author SHA1 Message Date
Clifford Wolf
397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf
48822e79a3 Removed left over debug code 2014-07-28 19:38:30 +02:00
Clifford Wolf
ec58965967 Fixed part selects of parameters 2014-07-28 19:24:28 +02:00
Clifford Wolf
a03297a7df Set results of out-of-bounds static bit/part select to undef 2014-07-28 16:09:50 +02:00
Clifford Wolf
55521c085a Fixed RTLIL code generator for part select of parameter 2014-07-28 15:31:19 +02:00
Clifford Wolf
0598bc8708 Fixed width detection for part selects 2014-07-28 15:19:34 +02:00
Clifford Wolf
27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf
3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
ee65dea738 Fixed signdness detection of expressions with bit- and part-selects 2014-07-28 10:10:08 +02:00
Clifford Wolf
c4bdba78cb Added proper Design->addModule interface 2014-07-27 21:12:09 +02:00
Clifford Wolf
7661ded8dd Fixed verific bindings for new RTLIL api 2014-07-27 12:00:28 +02:00
Clifford Wolf
6b34215efd Fixed ilang parser for new RTLIL API 2014-07-27 11:56:35 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf
97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf
309d64d46a Fixed two memory leaks in ast simplify 2014-07-25 13:24:10 +02:00
Clifford Wolf
1488bc0c4f Updated verific build/test instructions 2014-07-25 12:16:03 +02:00
Clifford Wolf
6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf
b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf
375aa71dfe Various fixes in Verific frontend for new RTLIL API 2014-07-23 21:35:01 +02:00
Clifford Wolf
20a7965f61 Various small fixes (from gcc compiler warnings) 2014-07-23 20:45:27 +02:00
Clifford Wolf
c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf
ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf
115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern 2014-07-22 23:50:21 +02:00
Clifford Wolf
28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only 2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf
3b5f4ff39c Fixed ilang parsing of process attributes 2014-07-22 20:39:37 +02:00
Clifford Wolf
d6d0e08834 Fixed make rules for ilang parser 2014-07-22 20:39:37 +02:00
Clifford Wolf
4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf
361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf
9b183539af Implemented dynamic bit-/part-select for memory writes 2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc Added support for bit/part select to mem2reg rewriter 2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8 Added support for constant bit- or part-select for memory writes 2014-07-17 13:13:21 +02:00
Clifford Wolf
b171a4c1bc Added "inout" ports support to read_liberty 2014-07-16 18:12:46 +02:00
Clifford Wolf
5057935722 Set blackbox attribute in "read_liberty -lib" 2014-07-16 18:12:16 +02:00
Clifford Wolf
24f58e57f3 Fixed spelling of "direction" in read_liberty messages 2014-07-16 18:02:28 +02:00
Clifford Wolf
543551b80a changes in verilog frontend for new $mem/$memwr WR_EN interface 2014-07-16 12:49:50 +02:00
Clifford Wolf
0f9ca49dc6 Added passing of various options to vhdl2verilog 2014-07-12 10:02:39 +02:00
Clifford Wolf
55a1b8dbac Fixed processing of initial values for block-local variables 2014-07-11 13:05:53 +02:00