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Refactoring: Renamed RTLIL::Design::modules to modules_
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parent
d088854b47
commit
10e5791c5e
73 changed files with 223 additions and 223 deletions
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@ -931,7 +931,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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(*it)->str = (*it)->str.substr(1);
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if (defer)
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(*it)->str = "$abstract" + (*it)->str;
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if (design->modules.count((*it)->str)) {
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if (design->modules_.count((*it)->str)) {
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if (!ignore_redef)
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log_error("Re-definition of module `%s' at %s:%d!\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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@ -939,7 +939,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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continue;
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}
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design->modules[(*it)->str] = process_module(*it, defer);
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design->modules_[(*it)->str] = process_module(*it, defer);
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}
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}
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@ -1036,10 +1036,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
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modname = "$paramod" + stripped_name + para_info;
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}
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if (design->modules.count(modname) == 0) {
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if (design->modules_.count(modname) == 0) {
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new_ast->str = modname;
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design->modules[modname] = process_module(new_ast, false);
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design->modules[modname]->check();
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design->modules_[modname] = process_module(new_ast, false);
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design->modules_[modname]->check();
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} else {
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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}
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@ -476,7 +476,7 @@ struct LibertyFrontend : public Frontend {
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std::string cell_name = RTLIL::escape_id(cell->args.at(0));
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if (design->modules.count(cell_name)) {
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if (design->modules_.count(cell_name)) {
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if (flag_ignore_redef)
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continue;
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
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@ -564,7 +564,7 @@ struct LibertyFrontend : public Frontend {
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}
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module->fixup_ports();
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design->modules[module->name] = module;
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design->modules_[module->name] = module;
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cell_count++;
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skip_cell:;
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}
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