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Use only module->addCell() and module->remove() to create and delete cells

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This commit is contained in:
Clifford Wolf 2014-07-25 15:05:18 +02:00
parent 5826670009
commit 2bec47a404
35 changed files with 259 additions and 582 deletions
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73
frontends/ast/genrtlil.cc
View file

@ -44,17 +44,11 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
cell->name = sstr.str();
cell->type = type;
current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire;
RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
wire->name = cell->name + "_Y";
wire->width = result_width;
current_module->wires[wire->name] = wire;
if (gen_attributes)
for (auto &attr : that->attributes) {
@ -84,17 +78,11 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
std::stringstream sstr;
sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
cell->name = sstr.str();
cell->type = celltype;
current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire;
RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
wire->name = cell->name + "_Y";
wire->width = width;
current_module->wires[wire->name] = wire;
if (that != NULL)
for (auto &attr : that->attributes) {
@ -119,17 +107,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
cell->name = sstr.str();
cell->type = type;
current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire;
RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
wire->name = cell->name + "_Y";
wire->width = result_width;
current_module->wires[wire->name] = wire;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@ -160,17 +142,11 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
cell->name = sstr.str();
cell->type = "$mux";
current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire;
RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", left.size());
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
wire->name = cell->name + "_Y";
wire->width = left.size();
current_module->wires[wire->name] = wire;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@ -1183,17 +1159,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr;
sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->name = sstr.str();
cell->type = "$memrd";
current_module->cells[cell->name] = cell;
RTLIL::Wire *wire = new RTLIL::Wire;
RTLIL::Wire *wire = current_module->addWire(cell->name + "_DATA", current_module->memories[str]->width);
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
wire->name = cell->name + "_DATA";
wire->width = current_module->memories[str]->width;
current_module->wires[wire->name] = wire;
int addr_bits = 1;
while ((1 << addr_bits) < current_module->memories[str]->size)
@ -1220,11 +1190,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr;
sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->name = sstr.str();
cell->type = "$memwr";
current_module->cells[cell->name] = cell;
int addr_bits = 1;
while ((1 << addr_bits) < current_module->memories[str]->size)
@ -1260,11 +1227,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
RTLIL::Cell *cell = new RTLIL::Cell;
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->name = sstr.str();
cell->type = "$assert";
current_module->cells[cell->name] = cell;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
@ -1297,9 +1261,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_CELL:
{
int port_counter = 0, para_counter = 0;
RTLIL::Cell *cell = new RTLIL::Cell;
if (current_module->count_id(str) != 0)
log_error("Re-definition of cell `%s' at %s:%d!\n",
str.c_str(), filename.c_str(), linenum);
RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
cell->name = str;
for (auto it = children.begin(); it != children.end(); it++) {
AstNode *child = *it;
if (child->type == AST_CELLTYPE) {
@ -1342,10 +1311,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
attr.first.c_str(), filename.c_str(), linenum);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
if (current_module->cells.count(cell->name) != 0)
log_error("Re-definition of cell `%s' at %s:%d!\n",
str.c_str(), filename.c_str(), linenum);
current_module->cells[str] = cell;
}
break;

5
frontends/ilang/parser.y
View file

@ -182,11 +182,8 @@ cell_stmt:
TOK_CELL TOK_ID TOK_ID EOL {
if (current_module->cells.count($3) != 0)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
current_cell = new RTLIL::Cell;
current_cell->type = $2;
current_cell->name = $3;
current_cell = current_module->addCell($3, $2);
current_cell->attributes = attrbuf;
current_module->cells[$3] = current_cell;
attrbuf.clear();
free($2);
free($3);

69
frontends/liberty/liberty.cc
View file

@ -54,48 +54,36 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_INV_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = A;
cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_XOR_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_AND_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_OR_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell);
return cell->connections["\\Y"];
}
@ -270,19 +258,14 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
}
}
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_INV_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = iq_sig;
cell->connections["\\Y"] = iqn_sig;
module->add(cell);
cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell = module->addCell(NEW_ID, "");
cell->connections["\\D"] = data_sig;
cell->connections["\\Q"] = iq_sig;
cell->connections["\\C"] = clk_sig;
module->add(cell);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@ -352,12 +335,9 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
}
}
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$_INV_";
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = iq_sig;
cell->connections["\\Y"] = iqn_sig;
module->add(cell);
if (clear_sig.size() == 1)
{
@ -366,12 +346,9 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = new RTLIL::Cell;
inv->name = NEW_ID;
inv->type = "$_INV_";
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
inv->connections["\\A"] = clear_sig;
inv->connections["\\Y"] = module->addWire(NEW_ID);
module->add(inv);
if (clear_polarity == true)
clear_negative = inv->connections["\\Y"];
@ -379,21 +356,15 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
clear_enable = inv->connections["\\Y"];
}
RTLIL::Cell *data_gate = new RTLIL::Cell;
data_gate->name = NEW_ID;
data_gate->type = "$_AND_";
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = clear_negative;
data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(data_gate);
RTLIL::Cell *enable_gate = new RTLIL::Cell;
enable_gate->name = NEW_ID;
enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = clear_enable;
enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(enable_gate);
}
if (preset_sig.size() == 1)
@ -403,12 +374,9 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = new RTLIL::Cell;
inv->name = NEW_ID;
inv->type = "$_INV_";
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
inv->connections["\\A"] = preset_sig;
inv->connections["\\Y"] = module->addWire(NEW_ID);
module->add(inv);
if (preset_polarity == false)
preset_positive = inv->connections["\\Y"];
@ -416,30 +384,21 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
preset_enable = inv->connections["\\Y"];
}
RTLIL::Cell *data_gate = new RTLIL::Cell;
data_gate->name = NEW_ID;
data_gate->type = "$_OR_";
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = preset_positive;
data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(data_gate);
RTLIL::Cell *enable_gate = new RTLIL::Cell;
enable_gate->name = NEW_ID;
enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = preset_enable;
enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(enable_gate);
}
cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N');
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->connections["\\D"] = data_sig;
cell->connections["\\Q"] = iq_sig;
cell->connections["\\E"] = enable_sig;
module->add(cell);
}
struct LibertyFrontend : public Frontend {