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https://github.com/YosysHQ/yosys
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Removed deprecated module->new_wire()
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parent
3cb61d03f8
commit
1d88f1cf9f
11 changed files with 47 additions and 56 deletions
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@ -227,8 +227,8 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
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static void create_ff(RTLIL::Module *module, LibertyAst *node)
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{
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RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig;
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bool clk_polarity = true, clear_polarity = true, preset_polarity = true;
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@ -309,8 +309,8 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
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static void create_latch(RTLIL::Module *module, LibertyAst *node)
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{
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RTLIL::SigSpec iq_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->new_wire(1, RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
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RTLIL::SigSpec iqn_sig(module->addWire(RTLIL::escape_id(node->args.at(1))));
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RTLIL::SigSpec enable_sig, data_sig, clear_sig, preset_sig;
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bool enable_polarity = true, clear_polarity = true, preset_polarity = true;
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@ -549,7 +549,7 @@ struct LibertyFrontend : public Frontend {
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}
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}
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if (!flag_lib || dir->value != "internal")
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module->new_wire(1, RTLIL::escape_id(node->args.at(0)));
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module->addWire(RTLIL::escape_id(node->args.at(0)));
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}
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for (auto node : cell->children)
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