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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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4
frontends/liberty/liberty.cc
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@ -239,7 +239,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
{
rerun_invert_rollback = false;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) {
clk_sig = it.second->get("\\A");
clk_polarity = !clk_polarity;
@ -316,7 +316,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
{
rerun_invert_rollback = false;
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) {
enable_sig = it.second->get("\\A");
enable_polarity = !enable_polarity;