mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-07 19:51:23 +00:00
Code Activity

Added RTLIL::Cell::has(portname)

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/ilang/parser.y
View file

@ -202,7 +202,7 @@ cell_body:
delete $5;
} |
cell_body TOK_CONNECT TOK_ID sigspec EOL {
if (current_cell->connections().count($3) != 0)
if (current_cell->has($3))
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
current_cell->set($3, *$4);
delete $4;