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Code Activity
15289 commits 122 branches 59 tags 72 MiB
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2011 commits

Author SHA1 Message Date
Miodrag Milanovic
477e43d921 Fix xilinx tests, when iopads are default 2019-12-21 13:18:44 +01:00
Eddie Hung
1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung
94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
Eddie Hung
d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570 
mem_arst.v: do not redeclare ANSI port
 2019-12-19 12:21:22 -05:00
Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung
aed67dd020 abc9 needs a clean afterwards 2019-12-16 18:42:23 -08:00
Eddie Hung
378d9e6e0c Add another test 2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f Accidentally commented out tests 2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5 Merge blockram tests 2019-12-16 13:01:51 -08:00
Diego H
87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
Diego H
f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236 Disable RAM16X1D test 2019-12-13 10:28:13 -08:00
Eddie Hung
d86d073ad6 Add testcase 2019-12-13 10:26:30 -08:00
Diego H
1c96345587 Renaming BRAM memory tests for the sake of uniformity 2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df Add #1460 testcase 2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6 Add test 2019-12-12 14:43:13 -08:00
Diego H
e33f407655 Adding a note (TODO) in the memory_params.ys check file 2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877 Even more obvious testcase 2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b Make testcase clearer with \o having its own init 2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19 Add test: 'Warning: ignoring initial value on non-register: \o' 2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung
705e520a52 Add a quick testcase for unknown modules as inout 2019-12-09 13:14:46 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f Fix for non-deterministic test 2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00