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Add unconditional match blocks for force RAM

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This commit is contained in:
Eddie Hung 2019-12-16 13:31:15 -08:00
parent 6b384861e4
commit 5a00d5578c
2 changed files with 47 additions and 6 deletions
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9
tests/arch/xilinx/blockram.ys
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@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 0 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
dump m:*
synth_xilinx -top sync_ram_sdp
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1