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Merge remote-tracking branch 'origin/master' into xaig_dff

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Eddie Hung 2019-12-12 14:57:17 -08:00
commit bea15b537b
18 changed files with 238 additions and 64 deletions
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83
tests/arch/ice40/ice40_opt.ys
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@ -1,3 +1,23 @@
read_verilog -icells -formal <<EOT
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
\$lut #(
.WIDTH(4),
.LUT(LUT)
) lut (
.A({I0,A,B,I3}),
.Y(O)
);
endmodule
EOT
design -stash unmap
read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0;
@ -20,7 +40,68 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut
# https://github.com/YosysHQ/yosys/issues/1543
design -reset
read_verilog <<EOT
module delay_element (input wire clk, input wire reset, input wire enable,
input wire chainin, output wire chainout, output reg latch);
reg const_zero = 0;
reg const_one = 1;
wire delay_tap;
//carry logic
(* keep *) SB_CARRY carry ( .CO(chainout), .I0(const_zero),
.I1(const_one), .CI(chainin));
//flip flop latch
(* keep *) SB_DFFER flipflop( .Q(latch), .C(clk), .E(enable),
.D(delay_tap), .R(reset));
//LUT table
// the LUT should just echo the carry in (I3)
// carry I0 = LUT I1
// carry I1 = LUT I2
// carry in = LUT I3
// LUT_INIT[0] = 0
// LUT_INIT[1] = 0
// LUT_INIT[2] = 0
// LUT_INIT[3] = 0
// LUT_INIT[4] = 0
// LUT_INIT[5] = 0
// LUT_INIT[6] = 0
// LUT_INIT[7] = 0
// LUT_INIT[8] = 1
// LUT_INIT[9] = 1
// LUT_INIT[10] = 1
// LUT_INIT[11] = 1
// LUT_INIT[12] = 1
// LUT_INIT[13] = 1
// LUT_INIT[14] = 1
// LUT_INIT[15] = 1
(* keep *) SB_LUT4 lut( .O(delay_tap), .I0(const_zero), .I1(const_zero),
.I2(const_one), .I3(chainin));
//TODO: is this the right way round??
defparam lut.LUT_INIT=16'hFF00;
endmodule // delay_element
EOT
synth_ice40
select -assert-count 1 t:SB_LUT4
select -assert-count 1 t:SB_CARRY
select -assert-count 1 t:SB_CARRY a:keep %i
select -assert-count 1 t:SB_CARRY c:carry %i

54
tests/arch/ice40/ice40_wrapcarry.ys Normal file
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@ -0,0 +1,54 @@
read_verilog <<EOT
module top(input A, B, CI, output O, CO);
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(A),
.I2(B),
.I3(1'b0),
.O(O)
);
endmodule
EOT
ice40_wrapcarry
select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
design -reset
read_verilog <<EOT
module top(input A, B, CI, output O, CO);
(* foo = "bar", answer = 42, keep=0 *)
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
(* keep, blah="blah", answer = 43 *)
SB_LUT4 #(
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(A),
.I2(B),
.I3(1'b0),
.O(O)
);
endmodule
EOT
ice40_wrapcarry
select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
ice40_wrapcarry -unwrap
select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i

22
tests/arch/ice40/wrapcarry.ys
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@ -1,22 +0,0 @@
read_verilog <<EOT
module top(input A, B, CI, output O, CO);
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(A),
.I2(B),
.I3(1'b0),
.O(O)
);
endmodule
EOT
ice40_wrapcarry
select -assert-count 1 t:$__ICE40_CARRY_WRAPPER