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https://github.com/YosysHQ/yosys
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Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
This commit is contained in:
Eddie Hung
GitHub
commit
a73f96594f
13 changed files with 529 additions and 65 deletions
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@ -1,5 +1,5 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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@ -11,7 +11,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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cd lutram_1w1r
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select -assert-count 8 t:AL_MAP_LUT2
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select -assert-count 8 t:AL_MAP_LUT4
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42
tests/arch/common/lutram.v
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42
tests/arch/common/lutram.v
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@ -0,0 +1,42 @@
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module lutram_1w1r
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#(parameter D_WIDTH=8, A_WIDTH=6)
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(
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input [D_WIDTH-1:0] data_a,
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input [A_WIDTH:1] addr_a,
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input we_a, clk,
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output reg [D_WIDTH-1:0] q_a
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);
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// Declare the RAM variable
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reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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ram[addr_a] <= data_a;
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q_a <= ram[addr_a];
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end
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endmodule
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module lutram_1w3r
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#(parameter D_WIDTH=8, A_WIDTH=5)
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(
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input [D_WIDTH-1:0] data_a, data_b, data_c,
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input [A_WIDTH:1] addr_a, addr_b, addr_c,
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input we_a, clk,
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output reg [D_WIDTH-1:0] q_a, q_b, q_c
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);
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// Declare the RAM variable
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reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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ram[addr_a] <= data_a;
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q_a <= ram[addr_a];
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q_b <= ram[addr_b];
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q_c <= ram[addr_c];
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end
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endmodule
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@ -1,21 +0,0 @@
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module top
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(
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input [7:0] data_a,
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input [6:1] addr_a,
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input we_a, clk,
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output reg [7:0] q_a
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);
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// Declare the RAM variable
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reg [7:0] ram[63:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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begin
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ram[addr_a] <= data_a;
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q_a <= data_a;
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end
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q_a <= ram[addr_a];
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end
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endmodule
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@ -1,5 +1,5 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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@ -10,7 +10,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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cd lutram_1w1r
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select -assert-count 24 t:L6MUX21
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select -assert-count 71 t:LUT4
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select -assert-count 32 t:PFUMX
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@ -1,5 +1,5 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
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@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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cd lutram_1w1r
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_RAM_5K
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select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D
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@ -1,5 +1,5 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
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@ -12,7 +12,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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cd lutram_1w1r
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select -assert-count 8 t:RAM16S4
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# other logic present that is not simple
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#select -assert-none t:RAM16S4 %% t:* %D
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@ -1,5 +1,5 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
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@ -10,6 +10,6 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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cd lutram_1w1r
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select -assert-count 1 t:SB_RAM40_4K
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select -assert-none t:SB_RAM40_4K %% t:* %D
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34
tests/arch/xilinx/bug1460.ys
Normal file
34
tests/arch/xilinx/bug1460.ys
Normal file
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@ -0,0 +1,34 @@
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read_verilog <<EOT
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module register_file(
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input wire clk,
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input wire write_enable,
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input wire [63:0] write_data,
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input wire [4:0] write_reg,
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input wire [4:0] read1_reg,
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input wire [4:0] read2_reg,
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input wire [4:0] read3_reg,
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output reg [63:0] read1_data,
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output reg [63:0] read2_data,
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output reg [63:0] read3_data
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);
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reg [63:0] registers[0:31];
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always @(posedge clk) begin
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if (write_enable == 1'b1) begin
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registers[write_reg] <= write_data;
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end
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end
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always @(all) begin
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read1_data <= registers[read1_reg];
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read2_data <= registers[read2_reg];
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read3_data <= registers[read3_reg];
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end
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endmodule
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EOT
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synth_xilinx
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cd register_file
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select -assert-count 32 t:RAM32M
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select -assert-none t:* t:BUFG %d t:RAM32M %d
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137
tests/arch/xilinx/lutram.ys
Normal file
137
tests/arch/xilinx/lutram.ys
Normal file
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@ -0,0 +1,137 @@
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#read_verilog ../common/lutram.v
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#hierarchy -top lutram_1w1r -chparam A_WIDTH 4
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#proc
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#memory -nomap
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#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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#memory
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#opt -full
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#
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#miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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#
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#design -load postopt
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#cd lutram_1w1r
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#select -assert-count 1 t:BUFG
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#select -assert-count 8 t:FDRE
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#select -assert-count 8 t:RAM16X1D
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#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 5
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM32X1D
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select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM64X1D
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select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FDRE
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select -assert-count 4 t:RAM32M
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select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r -chparam A_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 1 t:BUFG
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select -assert-count 24 t:FDRE
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select -assert-count 8 t:RAM64M
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select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FDRE
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select -assert-count 1 t:RAM32M
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select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FDRE
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select -assert-count 2 t:RAM64M
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select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
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@ -1,17 +0,0 @@
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read_verilog ../common/memory.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDRE
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select -assert-count 8 t:RAM64X1D
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select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
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