Akash Levy
5f5ed1b29e
Merge upstream yosys
2025-04-21 17:36:24 -07:00
David Sawatzke
04098933c7
cxxrtl: Add internal cell "bwmux"
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Mirrors the implementation for the smt2 backend
Co-authored-by: Martin Povišer <povik@cutebit.org>
2025-04-16 13:58:08 +01:00
Akash Levy
e241c9d513
Merge branch 'YosysHQ:main' into main
2025-04-10 14:28:10 -07:00
Krystine Sherwin
cd3b914132
Reinstate #4768
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Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Akash Levy
06c614a010
Merge branch 'YosysHQ:main' into main
2025-04-07 07:28:06 -07:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection"
2025-04-07 12:11:55 +02:00
Akash Levy
0dab4308a3
Actual merge here
2025-04-06 18:53:43 -07:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
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Refactor full_selection
2025-04-05 14:15:27 +13:00
Akash Levy
f218b5ba58
Revert "Represent memory size with size_t"
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This reverts commit bb5f8415af
2025-04-04 03:20:07 -07:00
Akash Levy
bb5f8415af
Represent memory size with size_t
2025-04-04 02:04:34 -07:00
Akash Levy
95f489beec
Merge nice gzip refactor
2025-03-20 16:47:12 -07:00
Emil J. Tywoniak
4f3fdc8457
io: refactor string and file work into new unit
2025-03-19 13:43:42 +01:00
Akash Levy
1c0d4a43b3
Merge branch 'YosysHQ:main' into main
2025-03-14 18:07:55 -07:00
KrystalDelusion
9fa1f0e70c
Merge pull request #4567 from kivikakk/cxxrtl-escape-trailing
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cxxrtl: use octal encoding of non-printables.
2025-03-14 16:52:07 +13:00
Krystine Sherwin
46a311acb2
firrtl: Drop full_selection check
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Change `top` pointer default to `nullptr` to avoid issues with `Design->top_module()` only operating on the current selection.
Calls to other passes (`bmuxmap` etc) will only operate on the current selection, and may cause problems when those cells are unprocessed, but this is consistent with the other backends that only operate on the full designs and will hopefully be fixed in another PR soon :)
2025-03-14 14:08:56 +13:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
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Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Akash Levy
e4066b784d
Merge remote-tracking branch 'upstream/main'
2025-03-12 19:21:32 -07:00
KrystalDelusion
65748b8387
Merge pull request #4898 from Anhijkt/fix-xaiger-segfault
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write_xaiger: Detect and error on combinatorial loops
2025-03-13 10:49:48 +13:00
Akash Levy
e360511339
Merge branch 'YosysHQ:main' into main
2025-03-10 14:21:49 -07:00
Alain Dargelas
268459e00a
write_verilog -srcattronly option
2025-03-10 10:15:24 -07:00
Alain Dargelas
1b1882fe56
write_verilog -srcattronly option
2025-03-10 09:29:48 -07:00
Alain Dargelas
e35032f2f6
write_verilog -onlysrcattr option
2025-03-10 09:27:27 -07:00
N. Engelhardt
c74df780b7
Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial
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Docs: More on FunctionalIR
2025-03-10 15:05:55 +00:00
Anhijkt
a8052f653a
write_xaiger: Detect and error on combinatorial loops
2025-02-14 01:21:39 +02:00
Krystine Sherwin
fa2d45a922
smtr: Refactor write back into _eval and _initial
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Easier for comparisons, and the structure still works. (I don't remember why I moved away from it in the first place.)
2025-02-07 13:58:09 +13:00
Akash Levy
66186f11fd
Merge branch 'YosysHQ:main' into main
2025-01-30 14:00:19 -08:00
Robin Ole Heinemann
0ab13924a5
write_verilog: log_abort on unhandled $check flavor
2025-01-30 14:18:02 +00:00
Robin Ole Heinemann
2f11dc87c9
write_verilog: emit $check cell names as labels
2025-01-30 14:18:02 +00:00
Akash Levy
f403256a34
Merge branch 'YosysHQ:main' into main
2025-01-23 14:06:16 -08:00
Catherine
3076803c9e
write_json: missing \n in help text.
2025-01-23 05:17:52 +00:00
Akash Levy
5c514e00a4
Sync with upstream
2025-01-13 17:20:59 -08:00
N. Engelhardt
77b28442a5
emit $scopeinfo cells by default
2025-01-08 14:47:46 +01:00
N. Engelhardt
dab7905cbe
write_json: add option to include $scopeinfo cells
2025-01-08 13:33:56 +01:00
Krystine Sherwin
7698dfba5e
smtr: Fix help text
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Can't take both [selection] and [filename] optional arguments.
2025-01-06 14:31:50 +13:00
Akash Levy
33b3d933de
Merge branch 'YosysHQ:main' into main
2024-12-25 04:25:25 -08:00
Catherine
1ef4c7f565
yosys-smtbmc: add cvc5 to help text.
2024-12-25 04:59:02 +00:00
Akash Levy
1dcf75d175
Sync
2024-12-19 21:40:30 -08:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Akash Levy
caaef5ac14
Merge branch 'YosysHQ:main' into main
2024-12-11 12:00:34 -08:00
Martin Povišer
86fad8f6f5
Merge pull request #4803 from povik/write_verilog-buf
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write_verilog: Use assign for `$buf`
2024-12-10 20:10:58 +01:00
Martin Povišer
559209c856
abc_new: Fix PI confusion in whitebox model export
2024-12-10 14:27:29 +01:00
Martin Povišer
495a7805ec
aiger2: Support $extern: hierarchy
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`$extern:...` modules inserted by `techmap -extern` are special in the
regard that they have a private ID (starting with a dollar sign) but are
not an internal cell. Support those modules in xaiger export.
2024-12-10 14:27:29 +01:00
Martin Povišer
e7b21d2706
write_verilog: Use assign for $buf
2024-12-05 18:28:23 +01:00
Akash Levy
4356eae4c9
Yosys sync
2024-12-04 14:16:55 -08:00
Krystine Sherwin
e634e9c26b
aiger2: Resolve warnings
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- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
2024-12-03 14:01:57 +13:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Akash Levy
1a69c51c88
Merge branch 'YosysHQ:main' into main
2024-11-18 16:10:30 -08:00
KrystalDelusion
dcff8b0666
Merge pull request #4719 from AdamLee7/main
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add select option for write_json
2024-11-19 08:42:38 +13:00
Akash Levy
5210d8614c
Merge
2024-11-17 22:46:05 -08:00
Akash Levy
ace558e90c
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00
