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Author SHA1 Message Date
Akash Levy
780f1bd705 Smallfixes 2026-07-09 17:22:05 -07:00
Akash Levy
4288594422 Clean up opts and make slightly better 2026-07-09 16:56:09 -07:00
Akash Levy
7777605d53
Merge pull request #210 from Silimate/cleanup_new_ids
More NEW_ID cleanup
2026-07-09 00:59:20 -07:00
Akash Levy
fa30cb1eef Revert mux NEW_ID4 naming that broke equiv_opt tests
Mux/MuxGate helpers must keep NEW_ID for the result wire; using
NEW_ID4_SUFFIX(name) can alias the caller's cell name and corrupt
netlists. Also drop now-dead cells.empty guards in alumacc.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-08 23:44:16 -07:00
Akash Levy
a022ca524d Fix flaky opt_priokey -strict and cover binary exclusive scan
ASLR-dependent ConstEval seeding let E4 miss OOR counterexamples; use a
deterministic seed and force OOR key collisions. Add I9 (NB=12) for the
thermometer fallback path Greptile flagged.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-08 23:20:22 -07:00
Akash Levy
a0935a9e9e More NEW_ID cleanup 2026-07-08 23:09:00 -07:00
Akash Levy
665bd1099a opt_first_fit_alloc updates + tests + some nice refactoring 2026-07-08 22:33:13 -07:00
Akash Levy
0a69890e3f opt_prienc: require ConstEval fingerprint inputs to be a valid cut
The round-robin (and PE/CLZ/CTZ) fingerprints pin candidate request/
start/select signals as free ConstEval inputs and evaluate the encoder
output cone. ConstEval::eval() re-computes and re-set()s the FULL output
of every combinational cell it needs. If a pinned bit is a combinational
cell output and a sibling output bit of that same cell is pulled into the
cone, evaluating the sibling re-sets the pinned bit to the cell's real
value, contradicting the free value we pinned and tripping the assertion
`current_val[i].wire != NULL || current_val[i] == value[i]` in
kernel/consteval.h.

The earlier clean_set_signals() guard only rejected constant/aliased
bits; it did not ensure the pinned signals form a valid cut. Candidates
are gathered purely by width, so an internal combinational wire (e.g. a
slice of a wider arithmetic result) can be pinned, which is exactly what
crashed on veer_speed1/picorv32/murax/raygentop.

Add is_valid_consteval_cut(): a pinned bit is a safe leaf when it is a
primary input, sequential-cell output or undriven (absent from
bit_to_driver, which holds combinational drivers only); a combinational
output is safe only if that cell's entire output lies within the pinned
cut. Apply it in both fingerprint() and fingerprint_rr(). Declining an
unclean cut only forgoes a possible rewrite, never yields a wrong one,
and the intended arbiter inputs (request ports, idx_last flop outputs)
remain valid cuts so real round-robin patterns still rewrite.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-07 00:00:24 -07:00
Akash Levy
676ac184ed opt_prienc: guard ConstEval fingerprint inputs against constant/aliased bits
The round-robin detector fed sigmap(wire) signals straight into
ConstEval::set() while sweeping test vectors. On real designs a candidate
bus can have bits tied to constants, repeated bits, or a req/start pair
that alias to the same net after sigmap. ConstEval::set() asserts
(current_val[i].wire != NULL || current_val[i] == value[i]) when asked to
re-pin such a bit to a conflicting value, crashing the pass
(consteval.h:83) on designs like veer/picorv32/murax/raygentop under
formal synthesis.

Add clean_set_signals() and reject any fingerprint candidate whose
set-signals contain constant bits, repeated bits, or overlap each other,
in both the priority-encoder and round-robin paths. Skipping an unclean
candidate only forgoes a possible rewrite; it never produces an incorrect
one. Clean candidates (the intended patterns) are unaffected.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 21:35:51 -07:00
Akash Levy
087f5bd254
Merge pull request #202 from Silimate/akashlevy/qor-pattern-passes
opt: recognize three QoR logic-depth patterns
2026-07-06 13:56:29 -07:00
Akash Levy
f5c54e5905 opt_prienc: give each round-robin req candidate its own fingerprint budget
The max_pairs budget was a single running counter shared across all
req_wire iterations, so once a start-candidate-heavy first req size
exhausted it, every later req size broke on its first start candidate and
was silently skipped. Reset the budget per req_wire so all req sizes get
a fair chance. (Completeness only; fingerprint_rr still validates every
match, so this never affected correctness.)

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 13:28:54 -07:00
Akash Levy
00e48706df opt: recognize three QoR logic-depth patterns
Extend two existing opt passes and add one new pass to collapse
serial/dynamic-index structures that were leaving high logic depth:

- opt_first_fit_alloc: recognize the "coalesce-matrix" first-fit
  allocator variant (same_cat[i][k] coalescing gated on the leader's
  enable, driven from a raw input enable). Rewrite both the lane_slot
  allocation and the xbar field gather from one shared log-depth scan.

- opt_prienc: detect round-robin / rotated-priority scans (req scanned
  from idx_last downward with wraparound) and rewrite the depth-N
  idx--/req[idx] mux chain to rotate -> log-depth priority-encode ->
  unrotate.

- opt_priokey (new): recognize priority-by-key one-hot accumulators and
  replace each dynamic taken[key] read ($shiftx/$bmux) with the
  equivalent pairwise-key-compare reduction, dropping the wide dynamic
  indexing. Supports -strict for full-key-range formal validation.

Each includes self-contained tests (equiv_opt / sat -prove-asserts,
mux-bound and negative cases) in tests/opt/.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 12:56:38 -07:00
Akash Levy
80bc373519 carvenetlist: keep cone boundary gate; address review comments
Fix the failing regression test: the single-fanout passthrough removal was
shorting out a cone's only real gate (e.g. a lone $_NOT_ driving an output),
replacing it with a bare wire. That drops the gate entirely (nothing left to
characterize) and, for an inverter, silently drops the inversion, making the
carved cell inequivalent to the RTL. Only short a redundant re-driver whose
input is driven by another in-cone cell; keep a passthrough that reads a
primary input (the cell-under-test's boundary gate).

Also address Greptile review comments:
- fix swapped log_warning arguments in the split-boundary-port diagnostic.
- error out (instead of silently overwriting) when two cell groups rename to
  the same carved module name (e.g. slow_<enc> and fast_<enc> -> <enc>).
- derive pq_speed from the explicit "fast_" base prefix.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 09:13:18 -07:00
Akash Levy
19c28d0e00 Merge branch 'main' into carvenetlist 2026-07-06 08:37:13 -07:00
Akash Levy
63dd7b7ee9
Merge pull request #201 from Silimate/merge5
Merge from upstream
2026-07-06 08:30:57 -07:00
Akash Levy
a2e38e2022 Merge from upstream 2026-07-06 07:47:32 -07:00
Akash Levy
3aa52fb1e5 Pass carvenetlist 2026-07-06 07:44:01 -07:00
Akash Levy
bab0ee6bf8 Speed up opt_* using cut_region with shared_ce 2026-07-06 07:42:47 -07:00
Akash Levy
9d39a82587 Allow sim pass to handle 4-input gates 2026-07-06 07:41:08 -07:00
Akash Levy
b600028644 Reduce verbosity of opt_dff 2026-07-06 07:40:47 -07:00
Akash Levy
7166468c55 Naming improvements 2026-07-06 07:40:14 -07:00
Akash Levy
77cd9e1edc stat bugfix 2026-06-28 20:28:23 -07:00
Akash Levy
d0380bf8f0 New stat 2026-06-28 01:18:21 -07:00
Akash Levy
04a604f9fe Smallfix to simplemap 2026-06-26 11:41:04 -07:00
Akash Levy
e992e76eba
Merge pull request #195 from Silimate/merge3
Merge3
2026-06-25 05:29:55 -07:00
Akash Levy
3783a820ee Merge remote-tracking branch 'upstream' into merge3 2026-06-25 04:51:46 -07:00
Akash Levy
f3b5b8f2c0 Sim count overflow fix pow10 2026-06-25 02:57:14 -07:00
Akash Levy
139caf991c opt_compact_prefix: scope per-sweep clean to module, warn on non-convergence
Address review feedback on the fixpoint loop:
- Scope the per-sweep cleanup to the module under rewrite via
  Pass::call_on_module(..., "clean -purge") instead of running clean over
  the whole design selection. This avoids O(N^2) work across modules and
  keeps untouched modules' dangling cells until their own sweep, matching
  the original single-call behavior.
- Emit a log_warning if a module fails to reach a fixpoint within
  max_sweeps, so silent truncation of compaction is visible.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-24 23:52:30 -07:00
Akash Levy
da947b72d8 opt_compact_prefix fix 3 2026-06-24 22:40:21 -07:00
Akash Levy
9bfe32bffc Reduce port resize to warning 2026-06-24 17:21:38 -07:00
Miodrag Milanovic
fd3ec58055 Remove leftover use of log_id 2026-06-24 08:04:48 +02:00
KrystalDelusion
a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown
equiv_opt: Add ignore-unknown-cells
2026-06-23 19:58:30 +00:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Krystine Sherwin
de6aa77dc8
equiv_opt: Add ignore-unknown-cells 2026-06-23 10:54:00 +12:00
nella
3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index
Optimize upto vector indexing (Fix #892).
2026-06-22 09:05:26 +00:00
nella
6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup
Add warnings and errors to `sim -r` with VCD code path
2026-06-22 09:02:32 +00:00
Mohamed Gaber
0e7671c1b3 Merge remote-tracking branch 'origin/main' into update_from_upstream 2026-06-21 15:07:32 +03:00
Akash Levy
8cdbd62394 opt_first_fit_alloc: address Greptile review
- pack_lanes: assert elem_w < 32 and pack the full element width instead
  of silently dropping bits >= 31.
- Remove the dead `cell` struct member and its unused assignment in run()
  (every emit helper shadows it with its own local `cell`).
- Decorrelate the pseudo-random bc bits from en (independent mix) so they
  no longer share an LFSR bit (e.g. en[7]/bc[0] for n=8).
- Add purpose comments to fingerprint_dsel and lane_of_bit.

Declined the std::stoi/std::stoll arg-parsing suggestion: it matches the
established convention in sibling passes (opt_argmax, opt_priority_onehot).

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-21 01:21:06 -07:00
Akash Levy
dc995eba98 opt_first_fit_alloc 2026-06-21 00:56:39 -07:00
Mohamed Gaber
4db5fe5f6d
Merge remote-tracking branch 'silimate/main' into update_from_upstream 2026-06-19 00:07:08 +03:00
nella
2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer
proc_dlatch - infer $adlatch (Fix #5910).
2026-06-18 16:50:48 +00:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745
Fix  `chparam` values are unsigned when using read_verilog frontend
2026-06-18 16:50:22 +00:00
Akash Levy
fe9689eaaf Small update 2026-06-18 05:26:28 -07:00
Akash Levy
db7cfd404d Fix cut_region.h debug 2026-06-18 04:02:52 -07:00
Akash Levy
9df378f8ac opt_carry_select pass 2026-06-18 02:36:29 -07:00
Mohamed Gaber
a4042f69b1
passes/silimate: remove leftover Makefile.inc 2026-06-17 21:14:44 +03:00
Mohamed Gaber
98a1db2756
equiv_opt: support -ignore-unknown-cells 2026-06-17 21:10:02 +03:00
Mohamed Gaber
8267cf87b5
infer_ce: remove pass 2026-06-17 21:01:20 +03:00
Mohamed Gaber
bd7c32f8a6
CMake: Linux fixes + Merge fallout fix 2026-06-16 19:32:45 +03:00