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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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6
passes/cmds/check.cc
View file

@ -217,7 +217,7 @@ struct CheckPass : public Pass {
const int threshold = 1024;
// if the multiplication may overflow we will catch it here
// if the multiplication may overflow we will catch it here
if (in_widths + out_widths >= threshold)
return true;
@ -400,7 +400,7 @@ struct CheckPass : public Pass {
message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src);
if (!coarsened_cells.count(driver)) {
if (!coarsened_cells.count(driver)) {
MatchingEdgePrinter printer(message, sigmap, prev, bit);
printer.add_edges_from_cell(driver);
} else {
@ -414,7 +414,7 @@ struct CheckPass : public Pass {
std::string src_attr = wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr);
}
message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src);
message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src);
}
prev = bit;

4
passes/cmds/linecoverage.cc
View file

@ -90,7 +90,7 @@ struct CoveragePass : public Pass {
std::map<std::string, std::set<int>> uncovered_lines;
std::map<std::string, std::set<int>> all_lines;
for (auto module : design->modules())
{
log_debug("Module %s:\n", module);
@ -136,7 +136,7 @@ struct CoveragePass : public Pass {
fout << "DA:" << l << ",";
if (uncovered_lines.count(file_entry.first) && uncovered_lines[file_entry.first].count(l))
fout << "0";
else
else
fout << "1";
fout << "\n";
}

2
passes/cmds/linux_perf.cc
View file

@ -36,7 +36,7 @@ struct LinuxPerf : public Pass {
bool formatted_help() override
{
auto *help = PrettyHelp::get_current();
auto content_root = help->get_root();
content_root->usage("linux_perf [on|off]");

6
passes/cmds/logger.cc
View file

@ -106,7 +106,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-warn" && argidx+1 < args.size()) {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to warn list.\n", pattern);
log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern));
@ -118,7 +118,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-nowarn" && argidx+1 < args.size()) {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to nowarn list.\n", pattern);
log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern));
@ -130,7 +130,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-werror" && argidx+1 < args.size()) {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to werror list.\n", pattern);
log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern));

2
passes/cmds/select.cc
View file

@ -1472,7 +1472,7 @@ struct SelectPass : public Pass {
const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min";
if (common_flagset_tally > 1)
log_cmd_error("Options %s can not be combined.\n", common_flagset);
log_cmd_error("Options %s can not be combined.\n", common_flagset);
if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally)
log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset);

4
passes/cmds/setenv.cc
View file

@ -47,14 +47,14 @@ struct SetenvPass : public Pass {
std::string name = args[1];
std::string value = args[2];
if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2);
#if defined(_WIN32)
_putenv_s(name.c_str(), value.c_str());
#else
if (setenv(name.c_str(), value.c_str(), 1))
log_cmd_error("Invalid name \"%s\".\n", name);
#endif
}
} SetenvPass;

6
passes/cmds/timeest.cc
View file

@ -122,7 +122,7 @@ struct EstimateSta {
if (aigs.at(fingerprint).name.empty()) {
log_error("Unsupported cell '%s' in module '%s'",
cell->type.unescape(), m);
}
}
}
combinational.push_back(cell);
@ -217,9 +217,9 @@ struct EstimateSta {
if (!topo.sort())
log_error("Module '%s' contains combinational loops", m);
// now we determine how long it takes for signals to stabilize
// `levels` records the time after a clock edge after which a signal is stable
dict<std::tuple<SigBit, Cell *, AigNode *>, arrivalint> levels;

4
passes/memory/memory_libmap.cc
View file

@ -343,7 +343,7 @@ struct MemMapping {
rejected_cfg_debug_msgs += "\n";
}
}
void log_reject(const Ram &ram, const PortGroup &pg, int pvi, std::string message) {
if(ys_debug(1)) {
rejected_cfg_debug_msgs += stringf("can't map to option selection [");
@ -516,7 +516,7 @@ std::pair<bool, Const> search_for_attribute(Mem mem, IdString attr) {
for (SigBit bit: port.addr)
if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr));
return std::make_pair(false, Const());
}

2
passes/opt/muxpack.cc
View file

@ -159,7 +159,7 @@ struct MuxpackWorker
if (cell->type == ID($mux))
b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig)
sigbit_with_non_chain_users.insert(a_bit);

32
passes/opt/opt_balance_tree.cc
View file

@ -73,15 +73,15 @@ struct OptBalanceTreeWorker {
// Base case: if we have only one source, return it
if (sources.size() == 1)
return sources[0];
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -89,7 +89,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
@ -97,26 +97,26 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
}
// Recursive case: split sources into two groups and create subtrees
int mid = (sources.size() + 1) / 2;
vector<SigSpec> left_sources(sources.begin(), sources.begin() + mid);
vector<SigSpec> right_sources(sources.begin() + mid, sources.end());
SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell);
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -124,7 +124,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
@ -132,7 +132,7 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
@ -280,7 +280,7 @@ struct OptBalanceTreeWorker {
{
// Create a tree
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells);
// Build a vector of all source signals
vector<SigSpec> source_signals;
vector<bool> signed_flags;
@ -295,10 +295,10 @@ struct OptBalanceTreeWorker {
if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) {
continue;
}
// Create the balanced tree
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
@ -313,7 +313,7 @@ struct OptBalanceTreeWorker {
}
}
}
// Remove all consumed cells, which now have been replaced by trees
for (auto cell : consumed_cells)
module->remove(cell);

4
passes/opt/opt_hier.cc
View file

@ -75,7 +75,7 @@ struct ModuleIndex {
} else {
classes[pair.second[i]].append(pair.first[i]);
}
}
}
}
}
@ -217,7 +217,7 @@ struct UsageData {
for (auto port_name : module->ports) {
Wire *port = module->wire(port_name);
log_assert(port);
if (port->port_input && port->port_output) {
// ignore bidirectional: hard to come up with sound handling
continue;

2
passes/opt/opt_lut.cc
View file

@ -296,7 +296,7 @@ struct OptLutWorker
luts_dlogic_inputs.erase(lut);
module->remove(lut);
eliminated_count++;
if (limit > 0)
limit--;

2
passes/opt/opt_share.cc
View file

@ -445,7 +445,7 @@ struct OptSharePass : public Pass {
while (mux_port_offset + op_conn_width < mux_port_size &&
op_outsig_offset + op_conn_width < op_outsig_size &&
mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])
op_conn_width++;
op_conn_width++;
log_assert(op_conn_width >= 1);

8
passes/opt/peepopt_muldiv_c.pmg
View file

@ -55,19 +55,19 @@ code
int c_const_int = c_const.as_int(c_const_signed);
int b_const_int_shifted = b_const_int << offset;
// Helper lambdas for two's complement math
// Helper lambdas for two's complement math
auto sign2sComplement = [](auto value, int numBits) {
if (value & (1 << (numBits - 1))) {
return -1;
return -1;
} else {
return 1;
return 1;
}
};
auto twosComplement = [](auto value, int numBits) {
if (value & (1 << (numBits - 1))) {
return (~value) + 1; // invert bits before adding 1
} else {
return value;
return value;
}
};

4
passes/opt/peepopt_shiftadd.pmg
View file

@ -104,8 +104,8 @@ code
std::string location = shift->get_src_attribute();
if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) {
log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) "
"was ignored to avoid high resource usage, see help peepopt\n",
log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) "
"was ignored to avoid high resource usage, see help peepopt\n",
location.c_str(), log_signal(old_a), log_signal(var_signal), -offset);
reject;
}

2
passes/sat/cutpoint.cc
View file

@ -116,7 +116,7 @@ struct CutpointPass : public Pass {
for (auto bit : sigmap(conn.second))
if (bit.wire)
wire_drivers.insert(bit);
for (auto wire : module->wires())
if (wire->port_input)
for (auto bit : sigmap(wire))

2
passes/sat/qbfsat.h
View file

@ -132,7 +132,7 @@ struct QbfSolutionType {
//More importantly, we want to have the ability to port hole assignments to other modules with compatible
//hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match.
//
//Option 2 has the benefits previously described, but wire names can be changed automatically by
//Option 2 has the benefits previously described, but wire names can be changed automatically by
//optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC.
//
//The approach taken here is to allow both options. We write the assignment information for each bit of

48
passes/sat/sim.cc
View file

@ -155,7 +155,7 @@ void zinit(Const &v)
struct SimInstance
{
SimShared *shared;
std::string scope;
Module *module;
Cell *instance;
@ -183,7 +183,7 @@ struct SimInstance
State past_clk;
State past_ce;
State past_srst;
FfData data;
};
@ -1050,7 +1050,7 @@ struct SimInstance
}
}
}
for (auto signal : signal_database)
{
if (shared->hdlname && signal.first->name.isPublic() && signal.first->has_attribute(ID::hdlname)) {
@ -1182,7 +1182,7 @@ struct SimInstance
{
if (cell->is_mem_cell()) {
std::string memid = cell->parameters.at(ID::MEMID).decode_string();
for (auto &data : fst_memories[memid])
for (auto &data : fst_memories[memid])
{
std::string v = shared->fst->valueOf(data.second);
set_memory_state(memid, Const(data.first), Const::from_string(v));
@ -1399,7 +1399,7 @@ struct SimWorker : SimShared
}
for(auto& writer : outputfiles)
writer->write(use_signal);
if (writeback) {
pool<Module*> wbmods;
top->writeback(wbmods);
@ -1592,7 +1592,7 @@ struct SimWorker : SimShared
if (start_time.time < fst->getStartTime())
log_warning("Start time is before simulation file start time\n");
startCount = fst->getStartTime();
} else if (start_time.end)
} else if (start_time.end)
startCount = fst->getEndTime();
else {
startCount = start_time.time * pow10(start_time.scale - fst->getScale());
@ -1605,7 +1605,7 @@ struct SimWorker : SimShared
if (stop_time.time < fst->getStartTime())
log_warning("Stop time is before simulation file start time\n");
stopCount = fst->getStartTime();
} else if (stop_time.end)
} else if (stop_time.end)
stopCount = fst->getEndTime();
else {
stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale());
@ -1621,7 +1621,7 @@ struct SimWorker : SimShared
bool initial = true;
int cycle = 0;
log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
if (cycles_set)
if (cycles_set)
log(" for %d clock cycle(s)",numcycles);
log("\n");
bool all_samples = fst_clock.empty();
@ -1839,9 +1839,9 @@ struct SimWorker : SimShared
std::getline(f, line);
if (line.size()==0) continue;
if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
if (line[0]!='.')
curr_cycle = atoi(line.c_str()+1);
curr_cycle = atoi(line.c_str()+1);
else
curr_cycle = -1; // force detect change
@ -1907,7 +1907,7 @@ struct SimWorker : SimShared
log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod);
if (!c->is_mem_cell())
log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod);
Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
Const data = Const::from_string(parts[2]);
top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data);
@ -2252,7 +2252,7 @@ struct SimWorker : SimShared
if (start_time.time < fst->getStartTime())
log_warning("Start time is before simulation file start time\n");
startCount = fst->getStartTime();
} else if (start_time.end)
} else if (start_time.end)
startCount = fst->getEndTime();
else {
startCount = start_time.time * pow10(start_time.scale - fst->getScale());
@ -2265,7 +2265,7 @@ struct SimWorker : SimShared
if (stop_time.time < fst->getStartTime())
log_warning("Stop time is before simulation file start time\n");
stopCount = fst->getStartTime();
} else if (stop_time.end)
} else if (stop_time.end)
stopCount = fst->getEndTime();
else {
stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale());
@ -2280,7 +2280,7 @@ struct SimWorker : SimShared
int cycle = 0;
log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
if (cycles_set)
if (cycles_set)
log(" for %d clock cycle(s)",numcycles);
log("\n");
@ -2351,22 +2351,22 @@ struct SimWorker : SimShared
f << initstate.str();
f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename);
f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle);
f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n";
f << "\t\t\tend\n";
f << "\t\tend\n";
f << "\t\t$finish;\n";
f << "\tend\n";
f << "endmodule\n";
@ -2483,7 +2483,7 @@ struct FSTWriter : public OutputWriter
fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
fstWriterSetRepackOnClose(fstfile, 1);
worker->top->write_output_header(
[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
[this]() { fstWriterSetUpscope(fstfile); },
@ -2632,7 +2632,7 @@ struct AIWWriter : public OutputWriter
aiwfile << '0';
}
aiwfile << '\n';
}
}
}
std::ofstream aiwfile;
@ -3038,7 +3038,7 @@ struct Fst2TbPass : public Pass {
log("\n");
log(" -n <integer>\n");
log(" number of clock cycles to simulate (default: 20)\n");
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override

2
passes/sat/synthprop.cc
View file

@ -159,7 +159,7 @@ void SynthPropWorker::run()
if (tracing_data[module].names.size() == 0) return;
if (!reset_name.empty()) {
int width = tracing_data[module].names.size();
int width = tracing_data[module].names.size();
SigSpec reset = module->wire(reset_name);
reset.extend_u0(width, true);

2
passes/techmap/abc9.cc
View file

@ -398,7 +398,7 @@ struct Abc9Pass : public ScriptPass
log_error("Can't handle partially selected module %s!\n", mod);
std::string tempdir_name;
if (cleanup)
if (cleanup)
tempdir_name = get_base_tmpdir() + "/";
else
tempdir_name = "_tmp_";

2
passes/techmap/abc_new.cc
View file

@ -135,7 +135,7 @@ struct AbcNewPass : public ScriptPass {
void script() override
{
if (check_label("check")) {
run("abc9_ops -check");
run("abc9_ops -check");
}
if (check_label("prep_boxes")) {

4
passes/techmap/booth.cc
View file

@ -260,7 +260,7 @@ struct BoothPassWorker {
y_sz_revised = y_sz + 1;
} else {
x_sz_revised = y_sz;
}
}
} else {
if (x_sz % 2 != 0) {
y_sz_revised = x_sz + 1;
@ -804,7 +804,7 @@ struct BoothPassWorker {
c_result = c_wire;
debug_csa_trees[column_ix].push_back(csa);
csa_ix++;
csa_ix++;
if (var_ix <= column_bits.size() - 1)
carry_bits_to_sum.append(c_wire);

2
passes/techmap/dfflegalize.cc
View file

@ -139,7 +139,7 @@ struct DffLegalizePass : public Pass {
}
// Table of all supported cell types.
// First index in the array is one of the FF_* values, second
// First index in the array is one of the FF_* values, second
// index is the set of negative-polarity inputs (OR of NEG_*
// values), and the value is the set of supported init values
// (OR of INIT_* values).

4
passes/techmap/extract_counter.cc
View file

@ -326,12 +326,12 @@ int counter_tryextract(
return 24;
//Mux should have A driven by count Q, and B by muxy
//if A and B are swapped, CE polarity is inverted
if(sigmap(cemux->getPort(ID::B)) == muxy &&
if(sigmap(cemux->getPort(ID::B)) == muxy &&
sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = false;
}
else if(sigmap(cemux->getPort(ID::A)) == muxy &&
else if(sigmap(cemux->getPort(ID::A)) == muxy &&
sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = true;

4
passes/techmap/libparse.cc
View file

@ -652,7 +652,7 @@ LibertyAst *LibertyParser::parse(bool top_level)
return NULL;
if (tok != 'v') {
report_unexpected_token(tok);
report_unexpected_token(tok);
}
LibertyAst *ast = new LibertyAst;
@ -662,7 +662,7 @@ LibertyAst *LibertyParser::parse(bool top_level)
{
tok = lexer(str);
// allow both ';' and new lines to
// allow both ';' and new lines to
// terminate a statement.
if ((tok == ';') || (tok == 'n'))
break;

6
passes/techmap/lut2mux.cc
View file

@ -33,7 +33,7 @@ int lut2mux(Cell *cell, bool word_mode)
if (GetSize(sig_a) == 1)
{
if (!word_mode)
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
else
cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
}
@ -47,11 +47,11 @@ int lut2mux(Cell *cell, bool word_mode)
Const lut1 = lut.extract(0, GetSize(lut)/2);
Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode);
if (!word_mode)
cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
else
cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
}

2
passes/techmap/techmap.cc
View file

@ -333,7 +333,7 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c);
if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
c->attributes.erase(ID::techmap_chtype);