mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 03:35:40 +00:00
Code Activity

Merge pull request #210 from Silimate/cleanup_new_ids

Browse source 
More NEW_ID cleanup
This commit is contained in:
Akash Levy 2026-07-09 00:59:20 -07:00 • committed by GitHub
commit 7777605d53
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
8 changed files with 186 additions and 147 deletions
Download patch file Download diff file Expand all files Collapse all files

79
passes/techmap/alumacc.cc
View file

@ -52,7 +52,8 @@ struct AlumaccWorker
if (GetSize(cached_slt) == 0) {
get_of();
get_sf();
cached_slt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
Cell *cell = alu_cell;
cached_slt = cell->module->Xor(NEW_ID2_SUFFIX("slt"), cached_of, cached_sf); // SILIMATE: Improve the naming
}
return cached_slt;
@ -70,8 +71,9 @@ struct AlumaccWorker
if (GetSize(cached_sgt) == 0) {
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_slt, cached_eq);
cached_sgt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
Cell *cell = alu_cell;
SigSpec Or = cell->module->Or(NEW_ID2_SUFFIX("or"), cached_slt, cached_eq); // SILIMATE: Improve the naming
cached_sgt = cell->module->Not(NEW_ID2_SUFFIX("sgt"), Or, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
return cached_sgt;
@ -79,8 +81,9 @@ struct AlumaccWorker
if (GetSize(cached_gt) == 0) {
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
Cell *cell = alu_cell;
SigSpec Or = cell->module->Or(NEW_ID2_SUFFIX("or"), cached_lt, cached_eq); // SILIMATE: Improve the naming
cached_gt = cell->module->Not(NEW_ID2_SUFFIX("gt"), Or, false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
return cached_gt;
@ -88,31 +91,37 @@ struct AlumaccWorker
}
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
if (GetSize(cached_eq) == 0) {
Cell *cell = alu_cell;
cached_eq = cell->module->ReduceAnd(NEW_ID2_SUFFIX("eq"), cell->getPort(ID::X), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
if (GetSize(cached_ne) == 0) {
Cell *cell = alu_cell;
cached_ne = cell->module->Not(NEW_ID2_SUFFIX("ne"), get_eq(), false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
return cached_ne;
}
RTLIL::SigSpec get_cf() {
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID::CO);
Cell *cell = alu_cell;
cached_cf = cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
cached_cf = cell->module->Not(NEW_ID2_SUFFIX("cf"), cached_cf[GetSize(cached_cf)-1], false, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
return cached_cf;
}
RTLIL::SigSpec get_of() {
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
Cell *cell = alu_cell;
cached_of = {cell->getPort(ID::CO), cell->getPort(ID::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
cached_of = cell->module->Xor(NEW_ID2_SUFFIX("of"), cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); // SILIMATE: Improve the naming
}
return cached_of;
}
@ -379,20 +388,21 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
auto cell = module->addCell(NEW_ID, ID($macc));
Cell *cell = n->cell;
Cell *new_cell = module->addCell(NEW_ID2_SUFFIX("macc"), ID($macc)); // SILIMATE: Improve the naming
macc_counter++;
log(" creating $macc cell for %s: %s\n", n->cell, cell);
log(" creating $macc cell for %s: %s\n", cell, new_cell);
for (auto attr: n->cell->attributes) {
cell->attributes[attr.first] = attr.second;
for (auto attr: cell->attributes) {
new_cell->attributes[attr.first] = attr.second;
}
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
cell->setPort(ID::Y, n->y);
cell->fixup_parameters();
module->remove(n->cell);
n->macc.to_cell(new_cell);
new_cell->setPort(ID::Y, n->y);
new_cell->fixup_parameters();
module->remove(cell);
delete n;
}
@ -446,7 +456,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEW_ID2_SUFFIX("alu_y"), max(GetSize(A), GetSize(B))); // SILIMATE: Improve the naming
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
@ -498,13 +508,14 @@ struct AlumaccWorker
for (auto &it1 : sig_alu)
for (auto n : it1.second)
{
log_assert(!n->cells.empty());
Cell *cell = n->cells[0];
if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
if (n->cells.size() > 0) {
for (auto attr : n->cells[0]->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
}
n->alu_cell = module->addPos(NEW_ID2_SUFFIX("pos"), n->a, n->y, n->is_signed); // SILIMATE: Improve the naming
for (auto attr : cell->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
log(" creating $pos cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
@ -514,7 +525,7 @@ struct AlumaccWorker
goto delete_node;
}
n->alu_cell = module->addCell(NEW_ID, ID($alu));
n->alu_cell = module->addCell(NEW_ID2_SUFFIX("alu"), ID($alu)); // SILIMATE: Improve the naming
alu_counter++;
log(" creating $alu cell for ");
@ -522,18 +533,16 @@ struct AlumaccWorker
log("%s%s", i ? ", ": "", n->cells[i]);
log(": %s\n", n->alu_cell);
if (n->cells.size() > 0) {
for (auto attr : n->cells[0]->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
}
for (auto attr : cell->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID2_SUFFIX("x"), GetSize(n->y))); // SILIMATE: Improve the naming
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID2_SUFFIX("co"), GetSize(n->y))); // SILIMATE: Improve the naming
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
@ -552,7 +561,7 @@ struct AlumaccWorker
if (cmp_ne) sig.append(n->get_ne());
if (GetSize(sig) > 1)
sig = module->ReduceOr(NEW_ID, sig);
sig = module->ReduceOr(NEW_ID2_SUFFIX("cmp_or"), sig); // SILIMATE: Improve the naming
sig.extend_u0(GetSize(cmp_y));
module->connect(cmp_y, sig);

20
passes/techmap/arith_tree.cc
View file

@ -295,7 +295,7 @@ struct ArithTreeWorker {
return true;
}
std::vector<CompressorTree::DepthSig> build_operand_pool(std::vector<Operand> &operands, int width, int &neg_compensation)
std::vector<CompressorTree::DepthSig> build_operand_pool(Cell *cell, std::vector<Operand> &operands, int width, int &neg_compensation)
{
// Expand operands into a flat list of signals for reduction
std::vector<CompressorTree::DepthSig> pool;
@ -306,7 +306,7 @@ struct ArithTreeWorker {
// Additive operand
op.sig.extend_u0(width, op.is_signed);
if (op.negate)
op.sig = module->Not(NEW_ID, op.sig);
op.sig = module->Not(NEW_ID2_SUFFIX("not"), op.sig); // SILIMATE: Improve the naming
pool.push_back({op.sig, 0});
} else {
// Multiplicative operand
@ -319,10 +319,10 @@ struct ArithTreeWorker {
}
auto [pa, pb] = CompressorTree::reduce_scheduled(module, pps, width, opt.strategy);
SigSpec p = module->addWire(NEW_ID, width);
module->addAdd(NEW_ID, pa, pb, p, false);
SigSpec np = module->addWire(NEW_ID, width);
module->addNot(NEW_ID, p, np);
SigSpec p = module->addWire(NEW_ID2_SUFFIX("prod"), width); // SILIMATE: Improve the naming
module->addAdd(NEW_ID2_SUFFIX("add"), pa, pb, p, false); // SILIMATE: Improve the naming
SigSpec np = module->addWire(NEW_ID2_SUFFIX("nprod"), width); // SILIMATE: Improve the naming
module->addNot(NEW_ID2_SUFFIX("not"), p, np); // SILIMATE: Improve the naming
pool.push_back({np, 0});
neg_compensation++;
}
@ -334,10 +334,10 @@ struct ArithTreeWorker {
return pool;
}
void emit_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation)
void emit_tree(Cell *cell, std::vector<Operand> &operands, SigSpec result_y, int neg_compensation)
{
int width = GetSize(result_y);
auto pool = build_operand_pool(operands, width, neg_compensation);
auto pool = build_operand_pool(cell, operands, width, neg_compensation);
int final_depth = 0;
auto [a, b] = CompressorTree::reduce_scheduled(module, std::move(pool), width, opt.strategy, nullptr, &final_depth);
auto final_choice = CompressorTree::pick_final_adder(width, final_depth, opt.final_mode);
@ -376,7 +376,7 @@ struct ArithTreeWorker {
for (auto c : chain)
to_remove.insert(c);
emit_tree(operands, root->getPort(ID::Y), neg_compensation);
emit_tree(root, operands, root->getPort(ID::Y), neg_compensation);
}
for (auto cell : to_remove)
@ -402,7 +402,7 @@ struct ArithTreeWorker {
continue;
if (!has_mul && operands.size() < 3)
continue;
emit_tree(operands, cell->getPort(ID::Y), neg_compensation);
emit_tree(cell, operands, cell->getPort(ID::Y), neg_compensation);
to_remove.insert(cell);
}
for (auto cell : to_remove)

17
passes/techmap/booth.cc
View file

@ -66,6 +66,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BoothPassWorker {
RTLIL::Module *module;
RTLIL::Cell *cell = nullptr;
SigMap sigmap;
int booth_counter;
bool lowpower = false;
@ -246,6 +247,8 @@ struct BoothPassWorker {
log("Mapping cell %s to %s Booth multiplier\n", cell, is_signed ? "signed" : "unsigned");
this->cell = cell;
// To simplify the generator size the arguments
// to be the same. Then allow logic synthesis to
// clean things up. Size to biggest
@ -290,7 +293,7 @@ struct BoothPassWorker {
int required_op_size = x_sz_revised + y_sz_revised;
if (required_op_size != z_sz) {
SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
SigSpec expanded_Y = module->addWire(NEW_ID2_SUFFIX("y"), required_op_size); // SILIMATE: Improve the naming
SigSpec Y_driver = expanded_Y;
Y_driver.extend_u0(Y.size(), is_signed);
module->connect(Y, Y_driver);
@ -399,7 +402,7 @@ struct BoothPassWorker {
if (mapped_cpa)
BuildCPA(module, wtree_a, wtree_b, Z);
else
module->addAdd(NEW_ID, wtree_a, wtree_b, Z);
module->addAdd(NEW_ID2_SUFFIX("cpa"), wtree_a, wtree_b, Z); // SILIMATE: Improve the naming
}
/*
@ -435,11 +438,11 @@ struct BoothPassWorker {
// append the sign bits
if (is_signed) {
SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0])));
ppij_vec.append({module->NotGate(NEW_ID, e), e, e});
SigBit e = module->XorGate(NEW_ID2_SUFFIX("e"), s_int[0], module->AndGate(NEW_ID2_SUFFIX("and"), X.msb(), module->OrGate(NEW_ID2_SUFFIX("or"), two_int[0], one_int[0]))); // SILIMATE: Improve the naming
ppij_vec.append({module->NotGate(NEW_ID2_SUFFIX("not"), e), e, e}); // SILIMATE: Improve the naming
} else {
// append the sign bits
ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]});
ppij_vec.append({module->NotGate(NEW_ID2_SUFFIX("not"), s_int[0]), s_int[0], s_int[0]}); // SILIMATE: Improve the naming
}
}
@ -469,7 +472,7 @@ struct BoothPassWorker {
one_int, two_int, s_int));
}
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int))));
ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID2_SUFFIX("xor"), sb_int, module->AndGate(NEW_ID2_SUFFIX("and"), X.msb(), module->OrGate(NEW_ID2_SUFFIX("or"), two_int, one_int)))); // SILIMATE: Improve the naming
ppij_vec.append(State::S1);
}
@ -722,7 +725,7 @@ struct BoothPassWorker {
// End Case
else if (n == s_vec.size() - 1) {
// Make the carry results.. Two extra bits after fa.
SigBit carry_out = module->addWire(NEW_ID, 1);
SigBit carry_out = module->addWire(NEW_ID2_SUFFIX("cpa_carry"), 1); // SILIMATE: Improve the naming
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],

10
passes/techmap/demuxmap.cc
View file

@ -57,17 +57,17 @@ struct DemuxmapPass : public Pass {
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID2_SUFFIX("eq"), sel, Const(i, GetSize(sel)), out[i]); // SILIMATE: Improve the naming
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
} else {
Wire *eq = module->addWire(NEW_ID);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
Wire *eq = module->addWire(NEW_ID2_SUFFIX("eq")); // SILIMATE: Improve the naming
RTLIL::Cell *eq_cell = module->addEq(NEW_ID2_SUFFIX("eq"), sel, Const(i, GetSize(sel)), eq); // SILIMATE: Improve the naming
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
RTLIL::Cell *mux = module->addMux(NEW_ID,
RTLIL::Cell *mux = module->addMux(NEW_ID2_SUFFIX("mux"),
Const(State::S0, width),
data,
eq,
out.extract(i*width, width));
out.extract(i*width, width)); // SILIMATE: Improve the naming
mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
}
}

64
passes/techmap/dfflegalize.cc
View file

@ -280,7 +280,10 @@ struct DffLegalizePass : public Pass {
void emulate_split_init_arst(FfData &ff) {
ff.remove();
FfData ff_dff(ff.module, &initvals, NEW_ID);
Module *module = ff.module;
IdString name = ff.name;
FfData ff_dff(module, &initvals, NEW_ID4_SUFFIX("dff")); // SILIMATE: Improve the naming
ff_dff.width = ff.width;
ff_dff.has_aload = ff.has_aload;
ff_dff.sig_aload = ff.sig_aload;
@ -293,11 +296,11 @@ struct DffLegalizePass : public Pass {
ff_dff.has_ce = ff.has_ce;
ff_dff.sig_ce = ff.sig_ce;
ff_dff.pol_ce = ff.pol_ce;
ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_dff.sig_q = module->addWire(NEW_ID4_SUFFIX("dff_q"), ff.width); // SILIMATE: Improve the naming
ff_dff.val_init = ff.val_init;
ff_dff.is_fine = ff.is_fine;
FfData ff_adff(ff.module, &initvals, NEW_ID);
FfData ff_adff(module, &initvals, NEW_ID4_SUFFIX("adff")); // SILIMATE: Improve the naming
ff_adff.width = ff.width;
ff_adff.has_aload = ff.has_aload;
ff_adff.sig_aload = ff.sig_aload;
@ -310,7 +313,7 @@ struct DffLegalizePass : public Pass {
ff_adff.has_ce = ff.has_ce;
ff_adff.sig_ce = ff.sig_ce;
ff_adff.pol_ce = ff.pol_ce;
ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_adff.sig_q = module->addWire(NEW_ID4_SUFFIX("adff_q"), ff.width); // SILIMATE: Improve the naming
ff_adff.val_init = Const(State::Sx, ff.width);
ff_adff.has_arst = true;
ff_adff.sig_arst = ff.sig_arst;
@ -318,9 +321,9 @@ struct DffLegalizePass : public Pass {
ff_adff.val_arst = ff.val_arst;
ff_adff.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(module, &initvals, NEW_ID4_SUFFIX("sel")); // SILIMATE: Improve the naming
ff_sel.width = 1;
ff_sel.sig_q = ff.module->addWire(NEW_ID);
ff_sel.sig_q = module->addWire(NEW_ID4_SUFFIX("sel_q")); // SILIMATE: Improve the naming
ff_sel.has_arst = true;
ff_sel.sig_arst = ff.sig_arst;
ff_sel.pol_arst = ff.pol_arst;
@ -329,9 +332,9 @@ struct DffLegalizePass : public Pass {
ff_sel.is_fine = ff.is_fine;
if (ff.is_fine)
ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
module->addMuxGate(NEW_ID4_SUFFIX("mux"), ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); // SILIMATE: Improve the naming
else
ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q);
module->addMux(NEW_ID4_SUFFIX("mux"), ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); // SILIMATE: Improve the naming
legalize_ff(ff_dff);
legalize_ff(ff_adff);
@ -392,7 +395,10 @@ struct DffLegalizePass : public Pass {
log_assert(ff.width == 1);
ff.remove();
FfData ff_clr(ff.module, &initvals, NEW_ID);
Module *module = ff.module;
IdString name = ff.name;
FfData ff_clr(module, &initvals, NEW_ID4_SUFFIX("clr")); // SILIMATE: Improve the naming
ff_clr.width = ff.width;
ff_clr.has_aload = ff.has_aload;
ff_clr.sig_aload = ff.sig_aload;
@ -409,11 +415,11 @@ struct DffLegalizePass : public Pass {
ff_clr.sig_arst = ff.sig_clr;
ff_clr.pol_arst = ff.pol_clr;
ff_clr.val_arst = Const(State::S0, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_clr.sig_q = module->addWire(NEW_ID4_SUFFIX("clr_q"), ff.width); // SILIMATE: Improve the naming
ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width);
ff_clr.is_fine = ff.is_fine;
FfData ff_set(ff.module, &initvals, NEW_ID);
FfData ff_set(module, &initvals, NEW_ID4_SUFFIX("set")); // SILIMATE: Improve the naming
ff_set.width = ff.width;
ff_set.has_aload = ff.has_aload;
ff_set.sig_aload = ff.sig_aload;
@ -430,25 +436,25 @@ struct DffLegalizePass : public Pass {
ff_set.sig_arst = ff.sig_set;
ff_set.pol_arst = ff.pol_set;
ff_set.val_arst = Const(State::S1, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_set.sig_q = module->addWire(NEW_ID4_SUFFIX("set_q"), ff.width); // SILIMATE: Improve the naming
ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width);
ff_set.is_fine = ff.is_fine;
FfData ff_sel(ff.module, &initvals, NEW_ID);
FfData ff_sel(module, &initvals, NEW_ID4_SUFFIX("sel")); // SILIMATE: Improve the naming
ff_sel.width = ff.width;
ff_sel.has_sr = true;
ff_sel.pol_clr = ff.pol_clr;
ff_sel.pol_set = ff.pol_set;
ff_sel.sig_clr = ff.sig_clr;
ff_sel.sig_set = ff.sig_set;
ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_sel.sig_q = module->addWire(NEW_ID4_SUFFIX("sel_q"), ff.width); // SILIMATE: Improve the naming
ff_sel.val_init = Const(initsel, ff.width);
ff_sel.is_fine = ff.is_fine;
if (!ff.is_fine)
ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
module->addMux(NEW_ID4_SUFFIX("mux"), ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); // SILIMATE: Improve the naming
else
ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q);
module->addMuxGate(NEW_ID4_SUFFIX("mux"), ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); // SILIMATE: Improve the naming
legalize_ff(ff_clr);
legalize_ff(ff_set);
@ -461,18 +467,21 @@ struct DffLegalizePass : public Pass {
log_assert(ff.has_aload);
log_assert(ff.width == 1);
Module *module = ff.module;
IdString name = ff.name;
auto active_high = [&](SigBit sig, bool pol) -> SigBit {
if (pol)
return sig;
return ff.is_fine ? ff.module->NotGate(NEW_ID, sig) : ff.module->Not(NEW_ID, sig)[0];
return ff.is_fine ? module->NotGate(NEW_ID4_SUFFIX("not"), sig) : module->Not(NEW_ID4_SUFFIX("not"), sig)[0]; // SILIMATE: Improve the naming
};
auto do_mux = [&](SigBit a, SigBit b, SigBit s) -> SigBit {
return ff.is_fine ? ff.module->MuxGate(NEW_ID, a, b, s) : ff.module->Mux(NEW_ID, a, b, s)[0];
return ff.is_fine ? module->MuxGate(NEW_ID4_SUFFIX("mux"), a, b, s) : module->Mux(NEW_ID4_SUFFIX("mux"), a, b, s)[0]; // SILIMATE: Improve the naming
};
auto do_or = [&](SigBit a, SigBit b) -> SigBit {
return ff.is_fine ? ff.module->OrGate(NEW_ID, a, b) : ff.module->Or(NEW_ID, a, b)[0];
return ff.is_fine ? module->OrGate(NEW_ID4_SUFFIX("or"), a, b) : module->Or(NEW_ID4_SUFFIX("or"), a, b)[0]; // SILIMATE: Improve the naming
};
SigBit en = active_high(ff.sig_aload, ff.pol_aload);
@ -898,11 +907,13 @@ struct DffLegalizePass : public Pass {
ff.sig_ad = State::S0;
ff.val_arst = State::S1;
ff.remove_init();
Wire *new_q = ff.module->addWire(NEW_ID);
Module *module = ff.module;
IdString name = ff.name;
Wire *new_q = module->addWire(NEW_ID4_SUFFIX("new_q")); // SILIMATE: Improve the naming
if (ff.is_fine)
ff.module->addNotGate(NEW_ID, new_q, ff.sig_q);
module->addNotGate(NEW_ID4_SUFFIX("not"), new_q, ff.sig_q); // SILIMATE: Improve the naming
else
ff.module->addNot(NEW_ID, new_q, ff.sig_q);
module->addNot(NEW_ID4_SUFFIX("not"), new_q, ff.sig_q); // SILIMATE: Improve the naming
ff.sig_q = new_q;
if (ff.val_init == State::S0)
ff.val_init = State::S1;
@ -994,10 +1005,13 @@ struct DffLegalizePass : public Pass {
sig = State::S1;
} else if (sig == State::S1) {
sig = State::S0;
} else if (ff.is_fine) {
sig = ff.module->NotGate(NEW_ID, sig);
} else {
sig = ff.module->Not(NEW_ID, sig);
Module *module = ff.module;
IdString name = ff.name;
if (ff.is_fine)
sig = module->NotGate(NEW_ID4_SUFFIX("not"), sig); // SILIMATE: Improve the naming
else
sig = module->Not(NEW_ID4_SUFFIX("not"), sig); // SILIMATE: Improve the naming
}
pol = !pol;
}

10
passes/techmap/dfflibmap.cc
View file

@ -536,25 +536,25 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, GetSize(old_sig));
sig = module->addWire(NEW_ID3_SUFFIX("qn"), GetSize(old_sig)); // SILIMATE: Improve the naming
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID::Y), sig);
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
it->setPort(ID::Y, module->addWire(NEW_ID3_SUFFIX("not_y"), GetSize(old_sig))); // SILIMATE: Improve the naming
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
module->addNotGate(NEW_ID3_SUFFIX("not"), sig, old_sig); // SILIMATE: Improve the naming
}
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);
sig = module->NotGate(NEW_ID3_SUFFIX("inv"), sig); // SILIMATE: Improve the naming
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
} else
if (port.second == 0) {
sig = module->addWire(NEW_ID);
sig = module->addWire(NEW_ID3_SUFFIX("nc")); // SILIMATE: Improve the naming
} else
log_abort();
new_cell->setPort("\\" + port.first, sig);

76
passes/techmap/extract_fa.cc
View file

@ -282,7 +282,7 @@ struct ExtractFaWorker
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
cell->setPort(ID::Y, module->addWire(NEW_ID2_SUFFIX("y"))); // SILIMATE: Improve the naming
module->connect(bit, new_driver);
}
}
@ -394,41 +394,47 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
Cell *cell = driver.at(*func3.at(key).at(func).begin());
Cell *fa = module->addCell(NEW_ID2_SUFFIX("fa"), ID($fa)); // SILIMATE: Improve the naming
fa->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
log(" Created $fa cell %s.\n", fa);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
fa->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID2_SUFFIX("inv_a"), A) : A); // SILIMATE: Improve the naming
fa->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID2_SUFFIX("inv_b"), B) : B); // SILIMATE: Improve the naming
fa->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID2_SUFFIX("inv_c"), C) : C); // SILIMATE: Improve the naming
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_ID2_SUFFIX("fa_x")); // SILIMATE: Improve the naming
Y = module->addWire(NEW_ID2_SUFFIX("fa_y")); // SILIMATE: Improve the naming
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
fa->setPort(ID::X, X);
fa->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
facache[fakey] = make_tuple(X, Y, fa);
}
bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
if (func3.at(key).count(xor3_func)) {
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
Cell *cell = driver.at(*func3.at(key).at(xor3_func).begin());
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID2_SUFFIX("not"), Y) : Y; // SILIMATE: Improve the naming
for (auto bit : func3.at(key).at(xor3_func))
assign_new_driver(bit, YY);
}
if (func3.at(key).count(xnor3_func)) {
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
Cell *cell = driver.at(*func3.at(key).at(xnor3_func).begin());
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID2_SUFFIX("not"), Y); // SILIMATE: Improve the naming
for (auto bit : func3.at(key).at(xnor3_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
{
Cell *cell = driver.at(*func3.at(key).at(func).begin());
SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID2_SUFFIX("not"), X) : X; // SILIMATE: Improve the naming
for (auto bit : func3.at(key).at(func))
assign_new_driver(bit, XX);
for (auto bit : func3.at(key).at(func))
assign_new_driver(bit, XX);
}
}
}
@ -501,38 +507,44 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID::WIDTH, 1);
Cell *cell = driver.at(*func2.at(key).at(func).begin());
Cell *fa = module->addCell(NEW_ID2_SUFFIX("fa"), ID($fa)); // SILIMATE: Improve the naming
fa->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
log(" Created $fa cell %s.\n", fa);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, State::S0);
fa->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID2_SUFFIX("inv_a"), A) : A); // SILIMATE: Improve the naming
fa->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID2_SUFFIX("inv_b"), B) : B); // SILIMATE: Improve the naming
fa->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_ID2_SUFFIX("fa_x")); // SILIMATE: Improve the naming
Y = module->addWire(NEW_ID2_SUFFIX("fa_y")); // SILIMATE: Improve the naming
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
fa->setPort(ID::X, X);
fa->setPort(ID::Y, Y);
}
if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y;
Cell *cell = driver.at(*func2.at(key).at(xor2_func).begin());
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID2_SUFFIX("not"), Y) : Y; // SILIMATE: Improve the naming
for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY);
}
if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y);
Cell *cell = driver.at(*func2.at(key).at(xnor2_func).begin());
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID2_SUFFIX("not"), Y); // SILIMATE: Improve the naming
for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY);
}
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
{
Cell *cell = driver.at(*func2.at(key).at(func).begin());
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID2_SUFFIX("not"), X) : X; // SILIMATE: Improve the naming
for (auto bit : func2.at(key).at(func))
assign_new_driver(bit, XX);
for (auto bit : func2.at(key).at(func))
assign_new_driver(bit, XX);
}
}
}
}

57
passes/techmap/maccmap.cc
View file

@ -27,9 +27,10 @@ struct MaccmapWorker
{
std::vector<std::set<RTLIL::SigBit>> bits;
RTLIL::Module *module;
RTLIL::Cell *cell;
int width;
MaccmapWorker(RTLIL::Module *module, int width) : module(module), width(width)
MaccmapWorker(RTLIL::Module *module, RTLIL::Cell *cell, int width) : module(module), cell(cell), width(width)
{
bits.resize(width);
}
@ -52,7 +53,7 @@ struct MaccmapWorker
a.extend_u0(width, is_signed);
if (do_subtract) {
a = module->Not(NEW_ID, a);
a = module->Not(NEW_ID2_SUFFIX("not"), a); // SILIMATE: Improve the naming
add(State::S1, 0);
}
@ -73,13 +74,13 @@ struct MaccmapWorker
for (int i = 0; i < GetSize(b); i++)
if (is_signed && i+1 == GetSize(b))
{
a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
a = {module->Not(NEW_ID2_SUFFIX("not"), a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; // SILIMATE: Improve the naming
add(module->And(NEW_ID2_SUFFIX("and"), a, RTLIL::SigSpec(b[i], width)), false, do_subtract); // SILIMATE: Improve the naming
add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract);
}
else
{
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
add(module->And(NEW_ID2_SUFFIX("and"), a, RTLIL::SigSpec(b[i], width)), false, do_subtract); // SILIMATE: Improve the naming
a = {a.extract(0, width-1), State::S0};
}
}
@ -108,16 +109,16 @@ struct MaccmapWorker
in3 = in3.extract(start_index, stop_index-start_index);
int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Wire *w1 = module->addWire(NEW_ID2_SUFFIX("fa_y"), width); // SILIMATE: Improve the naming
RTLIL::Wire *w2 = module->addWire(NEW_ID2_SUFFIX("fa_x"), width); // SILIMATE: Improve the naming
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
cell->setPort(ID::C, in3);
cell->setPort(ID::Y, w1);
cell->setPort(ID::X, w2);
RTLIL::Cell *fa = module->addCell(NEW_ID2_SUFFIX("fa"), ID($fa)); // SILIMATE: Improve the naming
fa->setParam(ID::WIDTH, width);
fa->setPort(ID::A, in1);
fa->setPort(ID::B, in2);
fa->setPort(ID::C, in3);
fa->setPort(ID::Y, w1);
fa->setPort(ID::X, w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb};
@ -237,14 +238,14 @@ struct MaccmapWorker
}
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
RTLIL::Cell *c = module->addCell(NEW_ID2_SUFFIX("alu"), ID($alu)); // SILIMATE: Improve the naming
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
c->setPort(ID::CI, State::S0);
c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID::X, module->addWire(NEW_ID, width));
c->setPort(ID::CO, module->addWire(NEW_ID, width));
c->setPort(ID::Y, module->addWire(NEW_ID2_SUFFIX("alu_y"), width)); // SILIMATE: Improve the naming
c->setPort(ID::X, module->addWire(NEW_ID2_SUFFIX("alu_x"), width)); // SILIMATE: Improve the naming
c->setPort(ID::CO, module->addWire(NEW_ID2_SUFFIX("alu_co"), width)); // SILIMATE: Improve the naming
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
@ -296,16 +297,16 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &term : macc.terms) {
summand_t this_summand;
if (GetSize(term.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEW_ID2_SUFFIX("mul"), width); // SILIMATE: Improve the naming
module->addMul(NEW_ID2_SUFFIX("mul"), term.in_a, term.in_b, this_summand.first, term.is_signed); // SILIMATE: Improve the naming
} else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) {
// Mimic old 'bit_terms' treatment in case it's relevant for performance,
// i.e. defer single-bit summands to be the last ones
bit_terms.append(term.in_a);
continue;
} else if (GetSize(term.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed);
this_summand.first = module->addWire(NEW_ID2_SUFFIX("pos"), width); // SILIMATE: Improve the naming
module->addPos(NEW_ID2_SUFFIX("pos"), term.in_a, this_summand.first, term.is_signed); // SILIMATE: Improve the naming
} else {
this_summand.first = term.in_a;
}
@ -325,14 +326,14 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (int i = 0; i < GetSize(summands); i += 2) {
if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEW_ID2_SUFFIX("sum"), width); // SILIMATE: Improve the naming
this_summand.second = summands[i].second && summands[i+1].second;
if (summands[i].second == summands[i+1].second)
module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addAdd(NEW_ID2_SUFFIX("add"), summands[i].first, summands[i+1].first, this_summand.first); // SILIMATE: Improve the naming
else if (summands[i].second)
module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first);
module->addSub(NEW_ID2_SUFFIX("sub"), summands[i+1].first, summands[i].first, this_summand.first); // SILIMATE: Improve the naming
else if (summands[i+1].second)
module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
module->addSub(NEW_ID2_SUFFIX("sub"), summands[i].first, summands[i+1].first, this_summand.first); // SILIMATE: Improve the naming
else
log_abort();
new_summands.push_back(this_summand);
@ -343,13 +344,13 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
if (summands.front().second)
module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y));
module->addNeg(NEW_ID2_SUFFIX("neg"), summands.front().first, cell->getPort(ID::Y)); // SILIMATE: Improve the naming
else
module->connect(cell->getPort(ID::Y), summands.front().first);
}
else
{
MaccmapWorker worker(module, width);
MaccmapWorker worker(module, cell, width);
RTLIL::SigSpec bit_terms;
for (auto &term : macc.terms) {