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https://github.com/YosysHQ/yosys
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opt_first_fit_alloc updates + tests + some nice refactoring
This commit is contained in:
Akash Levy
parent
ae74af906a
commit
665bd1099a
8 changed files with 1680 additions and 136 deletions
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@ -17,21 +17,25 @@
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*/
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// Shared cut-region matching infrastructure for the functional rewrite
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// passes (opt_argmax, opt_priority_onehot, opt_compact_prefix). These passes
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// find combinational regions between "cut" signals (module ports, FF data
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// pins, or internal buses), verify their function by ConstEval
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// fingerprinting, and replace the region while leaving surrounding logic
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// untouched.
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// passes (opt_argmax, opt_priority_onehot, opt_compact_prefix,
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// opt_first_fit_alloc). These passes find combinational regions between
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// "cut" signals (module ports, FF data pins, or internal buses), verify
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// their function by ConstEval fingerprinting, and replace the region while
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// leaving surrounding logic untouched.
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//
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// This header is designed to be included INSIDE each pass's private
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// namespace (after PRIVATE_NAMESPACE_BEGIN), so the shared code has a single
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// source without introducing link-level coupling between the passes.
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// Tiny shared helpers (is_sequential, clog2_int, const_u64, ...) live in
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// rewrite_utils.h so non-cut-region passes can share them too.
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//
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// All graph walks and fingerprint evaluations are charged against
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// per-module work budgets so that adversarial netlist shapes (deep shared
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// cones with hundreds of same-width candidate buses) degrade into skipped
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// candidates instead of multi-minute runtimes.
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#include "passes/opt/rewrite_utils.h"
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struct CutRegionWorker
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{
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struct RootCand {
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@ -93,25 +97,6 @@ struct CutRegionWorker
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build_indexes();
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}
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bool is_sequential(Cell *c)
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{
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return c->type.in(
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ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre),
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ID($_DFF_P_), ID($_DFF_N_),
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ID($_DFFE_PP_), ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
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ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_NN0_), ID($_DFF_NN1_),
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ID($dlatch), ID($adlatch), ID($dlatchsr),
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ID($mem), ID($mem_v2), ID($meminit), ID($meminit_v2),
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ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2),
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ID($fsm),
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ID($assert), ID($assume), ID($cover), ID($live), ID($fair),
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ID($print), ID($check),
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ID($anyconst), ID($anyseq), ID($allconst), ID($allseq),
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ID($initstate));
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}
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void build_indexes()
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{
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for (auto c : module->cells()) {
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@ -717,11 +702,7 @@ struct CutRegionWorker
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}
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for (auto c : module->cells()) {
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if (!c->type.in(ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre),
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ID($dlatch), ID($adlatch), ID($dlatchsr)))
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continue;
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if (!c->hasPort(ID::D))
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if (!is_storage_ff(c) || !c->hasPort(ID::D))
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continue;
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consider_root(sigmap(c->getPort(ID::D)), stringf("%s.D", log_id(c->name)), true);
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}
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@ -796,26 +777,6 @@ struct CutRegionWorker
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return roots;
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}
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// --- Small numeric helpers shared by the fingerprints. ---
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static uint64_t lowmask_u64(int w)
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{
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if (w <= 0)
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return 0;
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if (w >= 64)
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return ~0ULL;
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return (1ULL << w) - 1;
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}
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static Const const_u64(uint64_t value, int width)
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{
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vector<State> bits(width, State::S0);
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for (int i = 0; i < width && i < 64; i++)
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if ((value >> i) & 1ULL)
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bits[i] = State::S1;
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return Const(bits);
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}
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SigSpec zext_sig(SigSpec sig, int width)
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{
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sig = sigmap(sig);
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@ -28,19 +28,6 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static int clog2_int(int x)
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{
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int r = 0;
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while ((1 << r) < x)
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r++;
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return r;
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}
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static bool is_power_of_two(int x)
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{
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return x > 0 && (x & (x - 1)) == 0;
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}
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static Const packed_table_const(const vector<uint64_t> &values, int elem_width)
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{
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vector<State> bits(values.size() * elem_width, State::S0);
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File diff suppressed because it is too large
Load diff
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@ -25,6 +25,8 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/opt/rewrite_utils.h"
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// Priority-encoder variants the pass recognises.
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enum class PEVariant { NONE, CLZ_FULL, CLZ_SHORT, CTZ_FULL, CTZ_SHORT };
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@ -38,21 +40,6 @@ static const char* variant_name(PEVariant v) {
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}
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}
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static int clog2_int(int x) {
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int r = 0;
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while ((1 << r) < x) r++;
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return r;
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}
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// Build an N-bit Const from a uint64_t pattern. Bit i set in `pattern` -> bit i
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// of the result. Bits beyond 64 are zero.
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static Const u64_const(uint64_t pattern, int N) {
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std::vector<State> bits(N, State::S0);
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for (int i = 0; i < N && i < 64; i++)
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if ((pattern >> i) & 1ULL) bits[i] = State::S1;
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return Const(bits);
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}
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// Return the index of the highest set bit (MSB) of `c`, or -1 if all zero.
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static int const_msb_set(const Const& c, int N) {
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auto bits = c.to_bits();
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@ -99,24 +86,6 @@ struct OptPriEncWorker {
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OptPriEncWorker(Module* m) : module(m), sigmap(m) { build_indexes(); }
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bool is_sequential(Cell* c) {
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return c->type.in(
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ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre),
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ID($_DFF_P_), ID($_DFF_N_),
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ID($_DFFE_PP_), ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
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ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_NN0_), ID($_DFF_NN1_),
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ID($dlatch), ID($adlatch), ID($dlatchsr),
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ID($mem), ID($mem_v2), ID($meminit), ID($meminit_v2),
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ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2),
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ID($fsm),
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ID($assert), ID($assume), ID($cover), ID($live), ID($fair),
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ID($print), ID($check),
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ID($anyconst), ID($anyseq), ID($allconst), ID($allseq),
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ID($initstate));
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}
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void build_indexes() {
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for (auto cell : module->cells()) {
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if (is_sequential(cell)) {
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@ -213,7 +182,7 @@ struct OptPriEncWorker {
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// Build the test-vector deck for an N-bit input.
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vector<Const> gen_test_vectors(int N) {
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vector<Const> vs;
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vs.push_back(u64_const(0, N));
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vs.push_back(const_u64(0, N));
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for (int k = 0; k < N; k++) {
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std::vector<State> bits(N, State::S0);
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bits[k] = State::S1;
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@ -29,19 +29,6 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static int clog2_int(int x)
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{
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int r = 0;
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while ((1 << r) < x)
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r++;
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return r;
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}
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static bool is_power_of_two(int x)
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{
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return x > 0 && (x & (x - 1)) == 0;
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}
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// Pack a per-lane integer vector into a Const with elem_w bits per lane.
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static Const pack_lanes(const vector<int> &vals, int elem_w)
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{
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105
passes/opt/rewrite_utils.h
Normal file
105
passes/opt/rewrite_utils.h
Normal file
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@ -0,0 +1,105 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Silimate Inc. <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// Small shared helpers for Silimate functional-rewrite passes. Include inside
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// each pass's PRIVATE_NAMESPACE_BEGIN (same pattern as cut_region.h). Keep
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// cone/cut infrastructure in cut_region.h; put only type lists and tiny
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// numeric/Const helpers here so passes that do not use CutRegionWorker
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// (e.g. opt_prienc) can share them without pulling that machinery in.
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//
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// Guarded so a pass may include this directly and also via cut_region.h.
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#ifndef SILIMATE_REWRITE_UTILS_H
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#define SILIMATE_REWRITE_UTILS_H
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// Process-level / gate-level cells that terminate combinational cone walks.
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static inline bool is_sequential(Cell *c)
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{
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// Include $aldff/$aldffe: proc emits async-load FFs for async-reset
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// flops; opt later rewrites them to $adff. Omitting them lets get_cone
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// walk through the launch flop into D/CLK/ALOAD (e.g. full wdata).
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return c->type.in(
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ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($aldff), ID($aldffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre),
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ID($_DFF_P_), ID($_DFF_N_),
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ID($_DFFE_PP_), ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
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ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_NN0_), ID($_DFF_NN1_),
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ID($dlatch), ID($adlatch), ID($dlatchsr),
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ID($mem), ID($mem_v2), ID($meminit), ID($meminit_v2),
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ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2),
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ID($fsm),
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ID($assert), ID($assume), ID($cover), ID($live), ID($fair),
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ID($print), ID($check),
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ID($anyconst), ID($anyseq), ID($allconst), ID($allseq),
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ID($initstate));
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}
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// Clocked process-level FFs (no $ff, latches, or gate $_DFF_*). Used for
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// flop-D gather roots where Q/D semantics matter.
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static inline bool is_clocked_ff(Cell *c)
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{
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return c->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($aldff), ID($aldffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre));
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}
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// Storage cells whose D port is a useful rewrite root (clocked FFs + $ff +
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// latches). Broader than is_clocked_ff; narrower than is_sequential.
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static inline bool is_storage_ff(Cell *c)
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{
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return is_clocked_ff(c) ||
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c->type.in(ID($ff), ID($dlatch), ID($adlatch), ID($dlatchsr));
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}
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// Ceiling of log2(x) for x >= 1; clog2_int(1) == 0. Same as Yosys $clog2 for
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// positive widths used by these passes.
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static inline int clog2_int(int x)
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{
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int r = 0;
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while ((1 << r) < x)
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r++;
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return r;
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}
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static inline bool is_power_of_two(int x)
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{
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return x > 0 && (x & (x - 1)) == 0;
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}
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static inline uint64_t lowmask_u64(int w)
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{
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if (w <= 0)
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return 0;
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if (w >= 64)
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return ~0ULL;
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return (1ULL << w) - 1;
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}
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// Pack the low `width` bits of `value` into a Const (bit i <- value bit i).
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static inline Const const_u64(uint64_t value, int width)
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{
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vector<State> bits(width, State::S0);
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for (int i = 0; i < width && i < 64; i++)
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if ((value >> i) & 1ULL)
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bits[i] = State::S1;
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return Const(bits);
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}
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#endif // SILIMATE_REWRITE_UTILS_H
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@ -26,17 +26,6 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static int ceil_log2_int(int v)
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{
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int r = 0;
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int n = 1;
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while (n < v) {
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n <<= 1;
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r++;
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}
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return r;
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}
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#include "passes/opt/cut_region.h"
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struct OptCompactPrefixWorker : CutRegionWorker
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@ -788,7 +777,7 @@ struct OptCompactPrefixWorker : CutRegionWorker
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{
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ref_cell = rw.anchor;
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int width = GetSize(rw.root);
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int count_width = ceil_log2_int(width + 1);
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int count_width = clog2_int(width + 1);
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SigSpec in_s = sigmap(rw.a);
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vector<SigSpec> bits;
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@ -815,7 +804,7 @@ struct OptCompactPrefixWorker : CutRegionWorker
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int width = GetSize(rw.root);
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int loop_width = rw.loop_width;
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bool en_high = rw.msb_first; // polarity flag (see matching loop)
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int count_width = ceil_log2_int(loop_width + 1);
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int count_width = clog2_int(loop_width + 1);
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SigSpec dis_s = sigmap(rw.a);
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SigSpec data_s = sigmap(rw.b);
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@ -863,7 +852,7 @@ struct OptCompactPrefixWorker : CutRegionWorker
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SigSpec n_s = sigmap(rw.b);
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bool msb_first = rw.msb_first;
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int cnt_width = ceil_log2_int(width + 1);
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int cnt_width = clog2_int(width + 1);
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int table_size = 1 << cnt_width;
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int cmp_width = std::max(GetSize(n_s), cnt_width);
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@ -933,7 +922,7 @@ struct OptCompactPrefixWorker : CutRegionWorker
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{
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ref_cell = rw.anchor;
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int width = GetSize(rw.root);
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int cnt_width = ceil_log2_int(width + 1);
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int cnt_width = clog2_int(width + 1);
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SigSpec en_s = sigmap(rw.a);
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SigSpec data_s = sigmap(rw.b);
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@ -857,3 +857,317 @@ design -load postopt
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select -assert-min 1 w:*ffa_*
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design -reset
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log -pop
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# ============================================================================
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# Group I: exclusive saturating first-fit (no category / broadcast)
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# ============================================================================
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#
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# Plain taken[]/done[] scan without same-cat coalescing: each enabled lane
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# takes the next free slot until NB slots are exhausted. Later requesters get
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# rank 0 / not done. This is the qor_vmw_slot_lane shape.
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# I1: exclusive dsel-only, N=8 NB=4 (equiv + fires).
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log -header "I1: exclusive saturating allocator N=8 NB=4 (equiv)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top #(parameter N=8, NB=4, W=2) (
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input logic mode,
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input logic [N-1:0] req,
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output logic [N*W-1:0] dsel_flat
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);
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logic [N-1:0] en = req & {N{mode}};
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logic [W-1:0] dsel [0:N-1];
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logic [NB-1:0] taken;
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logic [N-1:0] done;
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always_comb begin
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for (int i=0;i<N;i++) dsel[i] = '0;
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taken = '0; done = '0;
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for (int i=0;i<N;i++)
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if (en[i])
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for (int j=0;j<NB;j++)
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if (!taken[j] && !done[i]) begin
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dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
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end
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end
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for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
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endmodule
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EOF
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hierarchy -top top
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proc
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opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I2: exclusive with raw-input enable + sibling done bus, N=16 NB=4.
|
||||
log -header "I2: exclusive N=16 NB=4 raw-input en + done (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=16, NB=4, W=2) (
|
||||
input logic [N-1:0] lane_en,
|
||||
output logic [N*W-1:0] dsel_flat,
|
||||
output logic [N-1:0] done_o
|
||||
);
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (lane_en[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
assign done_o = done;
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I3: exclusive with non-power-of-two slot budget (NB=3, W=2) -- learn nb=3.
|
||||
log -header "I3: exclusive NB=3 (non-power-of-two) N=8 (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=8, NB=3, W=2) (
|
||||
input logic [N-1:0] lane_en,
|
||||
output logic [N*W-1:0] dsel_flat
|
||||
);
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (lane_en[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I4: exclusive last-fit near-miss (scan slots NB-1..0) -> no rewrite.
|
||||
log -header "I4: exclusive last-fit near-miss -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=8, NB=4, W=2) (
|
||||
input logic [N-1:0] lane_en,
|
||||
output logic [N*W-1:0] dsel_flat
|
||||
);
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (lane_en[i])
|
||||
for (int j=NB-1;j>=0;j--)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
opt_first_fit_alloc
|
||||
select -assert-count 0 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I5: exclusive MSB-first scan (lanes N-1..0), N=8 NB=4 (equiv).
|
||||
log -header "I5: exclusive MSB-first scan N=8 NB=4 (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=8, NB=4, W=2) (
|
||||
input logic [N-1:0] lane_en,
|
||||
output logic [N*W-1:0] dsel_flat
|
||||
);
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=N-1;i>=0;i--)
|
||||
if (lane_en[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I6: exclusive + identity gather of wide lane payloads into NB slots
|
||||
# (qor_vmw_slot_lane shape: slot_data[j] = data[leader at j]).
|
||||
# DW != N so per-lane data buses are not mistaken for width-N enables.
|
||||
log -header "I6: exclusive + identity gather N=8 NB=4 DW=16 (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=8, NB=4, W=2, DW=16) (
|
||||
input logic [N-1:0] lane_en,
|
||||
input logic [N*DW-1:0] data_flat,
|
||||
output logic [N*W-1:0] dsel_flat,
|
||||
output logic [NB*DW-1:0] slot_flat
|
||||
);
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [DW-1:0] data [0:N-1];
|
||||
logic [DW-1:0] slot_data [0:NB-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
for (genvar g=0;g<N;g++) assign data[g] = data_flat[g*DW +: DW];
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
for (int j=0;j<NB;j++) slot_data[j] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (lane_en[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
slot_data[j] = data[i];
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
for (genvar g=0;g<NB;g++) assign slot_flat[g*DW +: DW] = slot_data[g];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I7: exclusive and2 enable (req = a & b), with sibling done — the
|
||||
# qor_vmw_slot_lane enable shape after opt folds the named `req` wire.
|
||||
# Equiv covers the and2 fingerprint path; I6 already covers identity gather.
|
||||
log -header "I7: exclusive and2 enable + done N=16 NB=4 (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=16, NB=4, W=2) (
|
||||
input logic [N-1:0] a,
|
||||
input logic [N-1:0] b,
|
||||
output logic [N*W-1:0] dsel_flat,
|
||||
output logic [N-1:0] done_o
|
||||
);
|
||||
logic [N-1:0] en = a & b;
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0; done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (en[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
assign done_o = done;
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# I8: exclusive and2 enable without a global `opt` — launch flop stays a
|
||||
# plain $dff (sync reset) so leaf runs are data_q halves. Covers the pre-opt
|
||||
# and2 path; $aldff sequential handling is exercised by qor_vmw_slot_lane.
|
||||
log -header "I8: exclusive and2 enable pre-opt N=8 NB=4 (equiv)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module top #(parameter N=8, NB=4, W=2) (
|
||||
input logic clk,
|
||||
input logic [2*N-1:0] wdata,
|
||||
output logic [N*W-1:0] dsel_flat
|
||||
);
|
||||
logic [2*N-1:0] data_q;
|
||||
always_ff @(posedge clk)
|
||||
data_q <= wdata;
|
||||
wire [N-1:0] req = data_q[N-1:0] & data_q[2*N-1:N];
|
||||
logic [W-1:0] dsel [0:N-1];
|
||||
logic [NB-1:0] taken;
|
||||
logic [N-1:0] done;
|
||||
always_comb begin
|
||||
for (int i=0;i<N;i++) dsel[i] = '0;
|
||||
taken = '0;
|
||||
done = '0;
|
||||
for (int i=0;i<N;i++)
|
||||
if (req[i])
|
||||
for (int j=0;j<NB;j++)
|
||||
if (!taken[j] && !done[i]) begin
|
||||
dsel[i] = W'(j); done[i] = 1'b1; taken[j] = 1'b1;
|
||||
end
|
||||
end
|
||||
for (genvar g=0;g<N;g++) assign dsel_flat[g*W +: W] = dsel[g];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
# Intentionally no `opt`.
|
||||
check -assert
|
||||
equiv_opt -assert opt_first_fit_alloc
|
||||
design -load postopt
|
||||
select -assert-min 1 w:*ffa_*
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue