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Revert mux NEW_ID4 naming that broke equiv_opt tests

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Mux/MuxGate helpers must keep NEW_ID for the result wire; using
NEW_ID4_SUFFIX(name) can alias the caller's cell name and corrupt
netlists. Also drop now-dead cells.empty guards in alumacc.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Akash Levy 2026-07-08 23:44:16 -07:00
parent a0935a9e9e
commit fa30cb1eef
2 changed files with 13 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

18
kernel/rtlil.cc
View file

@ -3427,10 +3427,10 @@ DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const std::string &src) { \
Module *module = this; \
RTLIL::SigSpec sig_y = addWire(NEW_ID4_SUFFIX("y"), sig_a.size()); \
RTLIL::SigSpec sig_y = addWire(!_pmux ? NEW_ID : NEW_ID4_SUFFIX("y"), sig_a.size()); \
add ## _func(name, sig_a, sig_b, sig_s, sig_y, src); \
return sig_y; \
} // SILIMATE: Improve the naming
} // SILIMATE: Improve the naming (NOT IMPROVED FOR MUX!)
DEF_METHOD(Mux, ID($mux), 0)
DEF_METHOD(Bwmux, ID($bwmux), 0)
DEF_METHOD(Pmux, ID($pmux), 1)
@ -3505,7 +3505,7 @@ DEF_METHOD(Bweqx, ID($bweqx))
add ## _func(name, sig1, sig2, sig3, src); \
return sig3; \
} // SILIMATE: Improve the naming
#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4, _mux) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->setPort("\\" #_P1, sig1); \
@ -3517,10 +3517,10 @@ DEF_METHOD(Bweqx, ID($bweqx))
} \
RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const std::string &src) { \
Module *module = this; \
RTLIL::SigBit sig4 = addWire(NEW_ID4_SUFFIX(#_P4)); \
RTLIL::SigBit sig4 = addWire(_mux ? NEW_ID : NEW_ID4_SUFFIX(#_P4)); \
add ## _func(name, sig1, sig2, sig3, sig4, src); \
return sig4; \
} // SILIMATE: Improve the naming
} // SILIMATE: Improve the naming (NOT IMPROVED AT ALL!)
#define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigBit &sig1, const RTLIL::SigBit &sig2, const RTLIL::SigBit &sig3, const RTLIL::SigBit &sig4, const RTLIL::SigBit &sig5, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
@ -3548,10 +3548,10 @@ DEF_METHOD_3(XorGate, ID($_XOR_), A, B, Y)
DEF_METHOD_3(XnorGate, ID($_XNOR_), A, B, Y)
DEF_METHOD_3(AndnotGate, ID($_ANDNOT_), A, B, Y)
DEF_METHOD_3(OrnotGate, ID($_ORNOT_), A, B, Y)
DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y)
DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y)
DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y)
DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y)
DEF_METHOD_4(MuxGate, ID($_MUX_), A, B, S, Y, 1)
DEF_METHOD_4(NmuxGate, ID($_NMUX_), A, B, S, Y, 0)
DEF_METHOD_4(Aoi3Gate, ID($_AOI3_), A, B, C, Y, 0)
DEF_METHOD_4(Oai3Gate, ID($_OAI3_), A, B, C, Y, 0)
DEF_METHOD_5(Aoi4Gate, ID($_AOI4_), A, B, C, D, Y)
DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y)
#undef DEF_METHOD_2

12
passes/techmap/alumacc.cc
View file

@ -514,10 +514,8 @@ struct AlumaccWorker
if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID2_SUFFIX("pos"), n->a, n->y, n->is_signed); // SILIMATE: Improve the naming
if (n->cells.size() > 0) {
for (auto attr : n->cells[0]->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
}
for (auto attr : cell->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
log(" creating $pos cell for ");
for (int i = 0; i < GetSize(n->cells); i++)
@ -535,10 +533,8 @@ struct AlumaccWorker
log("%s%s", i ? ", ": "", n->cells[i]);
log(": %s\n", n->alu_cell);
if (n->cells.size() > 0) {
for (auto attr : n->cells[0]->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
}
for (auto attr : cell->attributes)
n->alu_cell->attributes[attr.first] = attr.second;
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);