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opt_carry_select pass
This commit is contained in:
Akash Levy
parent
d928afec67
commit
9df378f8ac
4 changed files with 518 additions and 0 deletions
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@ -18,6 +18,10 @@ match op
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// Select OP
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select op->type.in($add, $mul, $and, $or, $xor, $xnor)
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// Leave carry-select structures alone: folding `s ? (a+1) : a` back into
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// `a + s` would put a late select signal onto a wide ripple carry.
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filter !op->get_bool_attribute(\carry_select)
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// Set ports, allowing A and B to be swapped
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choice <IdString> A {\A, \B}
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define <IdString> B (A == \A ? \B : \A)
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@ -23,6 +23,7 @@ OBJS += passes/silimate/clkmerge.o
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OBJS += passes/silimate/opt_boundary.o
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OBJS += passes/silimate/opt_vps.o
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OBJS += passes/silimate/opt_compact_prefix.o
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OBJS += passes/silimate/opt_carry_select.o
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OBJS += passes/silimate/infer_icg.o
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OBJS += passes/silimate/opt_expand.o
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343
passes/silimate/opt_carry_select.cc
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343
passes/silimate/opt_carry_select.cc
Normal file
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@ -0,0 +1,343 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include <cmath>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Marks the incrementer/mux a carry-select rewrite emits so peepopt -muxorder
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// (which would otherwise fold `s ? (a+1) : a` back into `a + s`, putting the
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// late select on a wide ripple carry) leaves them alone.
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static const IdString kAttrCarrySelect = ID(carry_select);
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static inline double log2p1(int n) { return std::log2(double(std::max(1, n)) + 1.0); }
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// Heuristic, model-free per-cell delay used only to rank "early" vs "late"
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// operands. Mirrors opt_timing_balance's heuristic so the two passes agree on
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// which arrivals dominate.
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static double estimate_cell_delay(const Cell *cell, int out_width)
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{
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if (cell == nullptr)
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return 1.0;
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IdString t = cell->type;
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if (t.in(ID($add), ID($sub), ID($neg), ID($alu), ID($shl), ID($shr), ID($sshl), ID($sshr)))
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return log2p1(out_width);
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if (t.in(ID($mul), ID($div), ID($mod)))
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return out_width;
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if (t == ID($pmux)) {
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int s_width = cell->hasParam(ID::S_WIDTH) ? cell->getParam(ID::S_WIDTH).as_int() : 1;
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return log2p1(s_width);
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}
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if (t.in(ID($and), ID($or)))
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return 0.5;
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// $mux, $xor, $xnor, $not, gate-level $_*_ and everything else: one level.
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return 1.0;
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}
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struct OptCarrySelectWorker {
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Module *module;
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SigMap sigmap;
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CellTypes cell_types;
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dict<SigBit, Cell*> driver; // sigmap'd output bit -> driving cell
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dict<SigBit, double> arrival_cache; // memoized arrival per bit
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pool<SigBit> on_stack; // combinational-loop guard
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int max_narrow;
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int min_wide;
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double margin;
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int converted = 0;
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OptCarrySelectWorker(Module *m, int max_narrow, int min_wide, double margin)
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: module(m), sigmap(m), max_narrow(max_narrow), min_wide(min_wide), margin(margin)
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{
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cell_types.setup();
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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driver[bit] = cell;
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}
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bool is_boundary(Cell *cell) {
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if (cell == nullptr)
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return true;
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if (cell->get_bool_attribute(ID::keep) || cell->get_bool_attribute(ID::blackbox))
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return true;
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if (cell->is_builtin_ff())
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return true;
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr),
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ID($mem), ID($mem_v2), ID($memrd), ID($memrd_v2),
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ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
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return true;
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return !cell_types.cell_known(cell->type);
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}
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Cell *driver_of(SigBit bit) {
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auto it = driver.find(bit);
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return (it == driver.end()) ? nullptr : it->second;
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}
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// Explicit-stack post-order traversal so arbitrarily deep combinational cones
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// cannot overflow the C++ stack (worker threads can have small stacks).
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double arrival_bit(SigBit start) {
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start = sigmap(start);
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if (!start.wire)
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return 0.0;
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if (auto it = arrival_cache.find(start); it != arrival_cache.end())
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return it->second;
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struct Frame { SigBit bit; bool finalize; };
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std::vector<Frame> stack;
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stack.push_back({start, false});
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while (!stack.empty()) {
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Frame &top = stack.back();
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SigBit bit = top.bit;
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if (!bit.wire || arrival_cache.count(bit)) {
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stack.pop_back();
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continue;
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}
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Cell *drv = driver_of(bit);
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if (drv == nullptr || is_boundary(drv)) {
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arrival_cache[bit] = 0.0;
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stack.pop_back();
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continue;
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}
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if (!top.finalize) {
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// Expand: schedule finalize, then push not-yet-resolved inputs.
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top.finalize = true;
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on_stack.insert(bit);
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for (auto &conn : drv->connections())
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if (drv->input(conn.first))
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for (auto in_bit : sigmap(conn.second)) {
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if (!in_bit.wire || arrival_cache.count(in_bit))
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continue;
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if (on_stack.count(in_bit)) // combinational loop: break it
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continue;
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stack.push_back({in_bit, false});
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}
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continue;
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}
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// Finalize: all resolvable inputs are now cached.
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double max_in = 0.0;
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int out_width = 1;
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for (auto &conn : drv->connections())
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if (drv->output(conn.first))
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out_width = std::max(out_width, GetSize(conn.second));
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for (auto &conn : drv->connections())
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if (drv->input(conn.first))
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for (auto in_bit : sigmap(conn.second)) {
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auto it = arrival_cache.find(in_bit);
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if (it != arrival_cache.end())
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max_in = std::max(max_in, it->second);
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}
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arrival_cache[bit] = max_in + estimate_cell_delay(drv, out_width);
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on_stack.erase(bit);
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stack.pop_back();
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}
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return arrival_cache.at(start);
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}
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double arrival(const SigSpec &sig) {
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double t = 0.0;
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for (auto bit : sigmap(sig))
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t = std::max(t, arrival_bit(bit));
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return t;
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}
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// Decision record so we never iterate over a mutating cell list.
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struct Plan {
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Cell *add;
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bool wide_is_a;
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int k; // narrow width / split point
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int w; // result width
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};
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bool qualifies(Cell *c, Plan &plan) {
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if (c->type != ID($add))
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return false;
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if (c->get_bool_attribute(kAttrCarrySelect))
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return false;
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if (c->getParam(ID::A_SIGNED).as_bool() || c->getParam(ID::B_SIGNED).as_bool())
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return false; // v1: unsigned operands only (exact zero-extension)
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int a_w = c->getParam(ID::A_WIDTH).as_int();
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int b_w = c->getParam(ID::B_WIDTH).as_int();
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int w = c->getParam(ID::Y_WIDTH).as_int();
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bool wide_is_a = a_w >= b_w;
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int narrow_w = std::min(a_w, b_w);
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int k = narrow_w;
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if (k < 1 || k >= w)
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return false;
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if (k > max_narrow)
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return false;
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if (w - k < min_wide)
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return false;
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SigSpec wide_sig = c->getPort(wide_is_a ? ID::A : ID::B);
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SigSpec narrow_sig = c->getPort(wide_is_a ? ID::B : ID::A);
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double arr_wide = arrival(wide_sig);
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double arr_narrow = arrival(narrow_sig);
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if (arr_narrow <= arr_wide + margin)
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return false; // no timing benefit: narrow operand is not the late one
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plan.add = c;
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plan.wide_is_a = wide_is_a;
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plan.k = k;
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plan.w = w;
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return true;
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}
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void apply(const Plan &plan) {
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Cell *cell = plan.add;
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int k = plan.k;
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int w = plan.w;
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std::string src = cell->get_src_attribute();
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SigSpec wide_sig = cell->getPort(plan.wide_is_a ? ID::A : ID::B);
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SigSpec narrow_sig = cell->getPort(plan.wide_is_a ? ID::B : ID::A);
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SigSpec y = cell->getPort(ID::Y);
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// Zero-extend the wide operand to the full result width.
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SigSpec wext = wide_sig;
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wext.extend_u0(w, /*is_signed=*/false);
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SigSpec wlow = wext.extract(0, k);
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SigSpec whigh = wext.extract(k, w - k);
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// Low add: produces the low k sum bits plus the carry into bit k.
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Wire *losum = module->addWire(NEW_ID2_SUFFIX("cs_lo"), k + 1);
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module->addAdd(NEW_ID2_SUFFIX("cs_lo_add"), wlow, narrow_sig, SigSpec(losum), /*is_signed=*/false, src);
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SigSpec losum_low = SigSpec(losum).extract(0, k);
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SigBit carry = SigSpec(losum)[k];
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// High part precomputed from the (early) wide operand, then selected by
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// the (late) low carry: hi = carry ? (whigh + 1) : whigh.
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Wire *hiinc = module->addWire(NEW_ID2_SUFFIX("cs_hi_inc"), w - k);
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Cell *inc = module->addAdd(NEW_ID2_SUFFIX("cs_hi_inc_add"), whigh, SigSpec(State::S1), SigSpec(hiinc), /*is_signed=*/false, src);
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inc->set_bool_attribute(kAttrCarrySelect);
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Wire *hi = module->addWire(NEW_ID2_SUFFIX("cs_hi"), w - k);
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Cell *mux = module->addMux(NEW_ID2_SUFFIX("cs_hi_mux"), /*A=*/whigh, /*B=*/SigSpec(hiinc), /*S=*/carry, SigSpec(hi), src);
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mux->set_bool_attribute(kAttrCarrySelect);
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// Reassemble result and drive the original adder output.
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SigSpec result = losum_low;
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result.append(SigSpec(hi));
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module->connect(y, result);
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module->remove(cell);
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converted++;
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}
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void run() {
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vector<Cell*> adds;
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for (auto cell : module->cells())
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if (cell->type == ID($add))
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adds.push_back(cell);
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vector<Plan> plans;
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for (auto c : adds) {
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Plan plan;
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if (qualifies(c, plan))
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plans.push_back(plan);
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}
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for (auto &plan : plans)
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apply(plan);
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}
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};
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struct OptCarrySelectPass : public Pass {
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OptCarrySelectPass() : Pass("opt_carry_select",
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"decompose wide-early + narrow-late adders into carry-select form") {}
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void help() override {
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_carry_select [options] [selection]\n");
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log("\n");
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log("Rewrites a $add of the shape `wide_early + narrow_late` into a low add plus\n");
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log("a high carry-select. The low add absorbs the late, narrow operand and emits a\n");
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log("carry; the wide high half is precomputed from the early operand (as `hi` and\n");
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log("`hi + 1`) and selected by that carry through a single mux. This moves the wide\n");
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log("carry propagation onto the early operand, so the late operand only sees a\n");
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log("small add plus one mux instead of a full-width ripple carry.\n");
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log("\n");
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log("Only unsigned adders whose narrow operand arrives later (per a heuristic\n");
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log("logic-depth model) than the wide operand are rewritten, so adders that would\n");
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log("not benefit are left untouched. Emitted cells are tagged so peepopt -muxorder\n");
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log("does not fold the carry-select back into a late-carry ripple adder.\n");
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log("\n");
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log(" -max-narrow N\n");
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log(" only rewrite when the narrow operand width is <= N (default 16).\n");
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log("\n");
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log(" -min-wide N\n");
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log(" only rewrite when the wide (high) part width is >= N (default 8).\n");
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log("\n");
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log(" -margin F\n");
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log(" require narrow_arrival > wide_arrival + F (default 0.0).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing OPT_CARRY_SELECT pass (late-operand carry-select).\n");
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int max_narrow = 16;
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int min_wide = 8;
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double margin = 0.0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-max-narrow" && argidx + 1 < args.size()) {
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max_narrow = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-min-wide" && argidx + 1 < args.size()) {
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min_wide = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-margin" && argidx + 1 < args.size()) {
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margin = atof(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int total = 0;
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for (auto module : design->selected_modules()) {
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OptCarrySelectWorker worker(module, max_narrow, min_wide, margin);
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worker.run();
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total += worker.converted;
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}
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log("Converted %d adder(s) to carry-select form.\n", total);
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}
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} OptCarrySelectPass;
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PRIVATE_NAMESPACE_END
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170
tests/silimate/opt_carry_select.ys
Normal file
170
tests/silimate/opt_carry_select.ys
Normal file
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@ -0,0 +1,170 @@
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# Tests for opt_carry_select.
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# ---------------------------------------------------------------------------
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log -header "Functional equivalence: wide-early + narrow-late add"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module cs(input [31:0] a, input [4:0] c0, input [4:0] c1, output [31:0] y);
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wire [4:0] cause = c0 ^ c1; // small logic so the narrow operand arrives late
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assign y = a + cause;
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endmodule
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EOF
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proc; opt_clean
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rename cs gold
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read_verilog -sv <<EOF
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module cs(input [31:0] a, input [4:0] c0, input [4:0] c1, output [31:0] y);
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wire [4:0] cause = c0 ^ c1;
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assign y = a + cause;
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endmodule
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EOF
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proc; opt_clean
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opt_carry_select cs
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opt_clean cs
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rename cs gate
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miter -equiv -flatten -make_assert gold gate miter
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hierarchy -top miter
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proc; opt; memory; opt
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sat -prove-asserts -verify
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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log -header "Structural rewrite: low add + incrementer + select mux"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module cs(input [31:0] a, input [4:0] c0, input [4:0] c1, output [31:0] y);
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wire [4:0] cause = c0 ^ c1;
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assign y = a + cause;
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endmodule
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EOF
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proc; opt_clean
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select -assert-count 1 t:$add
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opt_carry_select
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opt_clean
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# original wide add -> low add + high incrementer, plus one select mux
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select -assert-count 2 t:$add
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select -assert-count 1 t:$mux
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design -reset
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log -pop
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# ---------------------------------------------------------------------------
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log -header "Survives peepopt -muxorder (carry_select guard)"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module cs(input [31:0] a, input [4:0] c0, input [4:0] c1, output [31:0] y);
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wire [4:0] cause = c0 ^ c1;
|
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assign y = a + cause;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select
|
||||
opt_clean
|
||||
# the high incrementer and select mux are tagged carry_select
|
||||
select -assert-count 2 a:carry_select
|
||||
peepopt -muxorder
|
||||
opt_clean
|
||||
# guard must keep the tagged cells: muxorder would otherwise fold
|
||||
# `c ? (hi+1) : hi` back into `hi + c` and strip these tagged cells
|
||||
select -assert-count 2 a:carry_select
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "Equivalence: 64-bit wide, 6-bit narrow-late operand"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input [63:0] a, input [5:0] c0, input [5:0] c1, output [63:0] y);
|
||||
wire [5:0] cause = c0 | c1;
|
||||
assign y = a + cause;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
rename cs gold
|
||||
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input [63:0] a, input [5:0] c0, input [5:0] c1, output [63:0] y);
|
||||
wire [5:0] cause = c0 | c1;
|
||||
assign y = a + cause;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select cs
|
||||
opt_clean cs
|
||||
rename cs gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "Negative: narrow operand is early (both direct inputs) -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input [31:0] a, input [4:0] c, output [31:0] y);
|
||||
assign y = a + c;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "Negative: equal-width operands (no narrow operand) -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input [31:0] a, input [31:0] b0, input [31:0] b1, output [31:0] y);
|
||||
wire [31:0] b = b0 ^ b1;
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select
|
||||
select -assert-count 0 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "Negative: signed operands -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input signed [31:0] a, input signed [4:0] c0, input signed [4:0] c1, output signed [31:0] y);
|
||||
wire signed [4:0] cause = c0 ^ c1;
|
||||
assign y = a + cause;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select
|
||||
select -assert-count 0 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
log -header "Negative: high part below min_wide -> no rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog -sv <<EOF
|
||||
module cs(input [9:0] a, input [4:0] c0, input [4:0] c1, output [9:0] y);
|
||||
wire [4:0] cause = c0 ^ c1; // w-k = 5 < default min_wide (8)
|
||||
assign y = a + cause;
|
||||
endmodule
|
||||
EOF
|
||||
proc; opt_clean
|
||||
opt_carry_select
|
||||
select -assert-count 0 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Add table
Add a link
Reference in a new issue