Merge pull request #195 from Silimate/merge3

Merge3
2026-07-15 03:35:40 +00:00 · 2026-06-25 05:29:55 -07:00 · 2026-06-25 05:29:55 -07:00 · e992e76eba
commit e992e76eba
parent 7449b008a4 3783a820ee
655 changed files with 11031 additions and 9437 deletions
--- a/.dockerignore
+++ b/.dockerignore
@ -1,12 +0,0 @@
-.editorconfig
-.gitignore
-.gitmodules
-.github
-.git
-Dockerfile
-README.md
-manual
-guidelines
-CodeOfConduct
-.travis
-.travis.yml
--- a/.github/ISSUE_TEMPLATE/config.yml
+++ b/.github/ISSUE_TEMPLATE/config.yml
@ -5,4 +5,3 @@ contact_links:
  - name: IRC Channel
    url: https://web.libera.chat/#yosys
    about: "#yosys on irc.libera.chat"
-
--- a/.github/ISSUE_TEMPLATE/feature_request.yml
+++ b/.github/ISSUE_TEMPLATE/feature_request.yml
@ -22,4 +22,3 @@ body:
      description: "A clear and detailed description of the feature."
    validations:
      required: true
-
--- a/.github/PULL_REQUEST_TEMPLATE.md
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@ -6,4 +6,4 @@ _Explain how this is achieved._

 _Make sure your change comes with tests. If not possible, share how a reviewer might evaluate it._

-_These template prompts can be deleted when you're done responding to them._
+_These template prompts can be deleted when you're done responding to them._
--- a/.github/workflows/extra-builds.yml
+++ b/.github/workflows/extra-builds.yml
@ -59,7 +59,6 @@ jobs:
          cmake -S . -B build
          -A x64
          -DCMAKE_BUILD_TYPE=Release
-          -DYOSYS_WITHOUT_ABC=ON

      - name: Build
        run: >
@ -67,6 +66,51 @@ jobs:
          --config Release
          --parallel

+  mingw-build:
+    name: MINGW64 build
+    runs-on: windows-latest
+    needs: [pre_job]
+    if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true'
+    steps:
+      - uses: actions/checkout@v5
+        with:
+          submodules: true
+          persist-credentials: false
+
+      - name: Setup MSYS2 (MINGW64)
+        uses: msys2/setup-msys2@v2
+        with:
+          msystem: MINGW64
+          update: true
+
+          install: >-
+            base-devel
+            mingw-w64-x86_64-toolchain
+            mingw-w64-x86_64-cmake
+            mingw-w64-x86_64-gtest
+            mingw-w64-x86_64-pkgconf
+            mingw-w64-x86_64-python
+            mingw-w64-x86_64-tcl
+            mingw-w64-x86_64-libffi
+            mingw-w64-x86_64-git
+
+          msys2-install: >-
+            bison
+            flex
+            gawk
+            diffutils
+            make
+
+      - name: Build Yosys
+        shell: msys2 {0}
+        run: |
+          set -e
+          procs=$(nproc)
+          rm -rf build
+          cmake -S . -B build -DCMAKE_BUILD_TYPE=Release
+          cmake --build build -j${procs}
+          ctest --test-dir build/tests/unit --output-on-failure
+
  wasi-build:
    name: WASI build
    needs: pre_job
@ -122,6 +166,7 @@ jobs:
    runs-on: ubuntu-latest
    needs:
      - vs-build
+      - mingw-build
      - wasi-build
      - nix-build
    if: always()
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@ -0,0 +1,30 @@
+# To use:
+#
+#     pre-commit run -a
+#
+# Or:
+#
+#     pre-commit install  # (runs every time you commit in git)
+#
+# To update this file:
+#
+#     pre-commit autoupdate
+#
+# See https://github.com/pre-commit/pre-commit
+
+exclude: ^libs/
+
+repos:
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v6.0.0
+  hooks:
+  - id: check-case-conflict
+  - id: check-executables-have-shebangs
+  - id: check-illegal-windows-names
+  - id: check-yaml
+    args: [--allow-multiple-documents]
+  - id: end-of-file-fixer
+  - id: fix-byte-order-marker
+  - id: mixed-line-ending
+    args: [--fix,lf]
+  - id: trailing-whitespace
--- a/45
+++ b/45
@ -11,7 +11,7 @@ Yosys 0.65 .. Yosys 0.66
    - C++ compiler with C++20 support is required.
    - Please be aware that next release will also
      migrate to CMake build system.
- 
+
 * New commands and options
    - Added "lattice_dsp_nexus" pass for Lattice Nexus
      DSP inference.
@ -78,7 +78,7 @@ Yosys 0.61 .. Yosys 0.62
      cascaded cells into tree of cells to improve timing.
    - Added "-gatesi" option to "write_blif" pass to init gates
      under gates_mode in BLIF format.
-    - Added "-on" and "-off" options to "debug" pass for 
+    - Added "-on" and "-off" options to "debug" pass for
      persistent debug logging.
    - Added "linux_perf" pass to control performance recording.

@ -92,7 +92,7 @@ Yosys 0.60 .. Yosys 0.61
 * New commands and options
    - Added "design_equal" pass to support fuzz-test comparison.
    - Added "lut2bmux" pass to convert $lut to $bmux.
-    - Added "-legalize" option to "read_rtlil" pass to prevent 
+    - Added "-legalize" option to "read_rtlil" pass to prevent
      semantic errors.

 Yosys 0.59 .. Yosys 0.60
@ -196,7 +196,7 @@ Yosys 0.53 .. Yosys 0.54
    - Enable single-bit vector wires in RTLIL.

 * Xilinx support
-    - Single-port URAM mapping to support memories 2048 x 144b 
+    - Single-port URAM mapping to support memories 2048 x 144b

 Yosys 0.52 .. Yosys 0.53
 --------------------------
@ -222,7 +222,7 @@ Yosys 0.51 .. Yosys 0.52
 --------------------------
 * New commands and options
    - Added "-pattern-limit" option to "share" pass to limit analysis effort.
-    - Added "libcache" pass to control caching of technology library 
+    - Added "libcache" pass to control caching of technology library
      data parsed from liberty files.
    - Added "read_verilog_file_list" to parse verilog file list.

@ -288,7 +288,7 @@ Yosys 0.47 .. Yosys 0.48

 * Gowin support
    - Added "-family" option to "synth_gowin" pass.
-    - Cell definitions split by family. 
+    - Cell definitions split by family.

 * Verific support
    - Improved blackbox support.
@ -315,7 +315,7 @@ Yosys 0.45 .. Yosys 0.46
    - Added new "functional backend" infrastructure with three example
      backends (C++, SMTLIB and Rosette).
    - Added new coarse-grain buffer cell type "$buf" to RTLIL.
-    - Added "-y" command line option to execute a Python script with 
+    - Added "-y" command line option to execute a Python script with
      libyosys available as a built-in module.
    - Added support for casting to type in Verilog frontend.

@ -323,7 +323,7 @@ Yosys 0.45 .. Yosys 0.46
    - Added "clockgate" pass for automatic clock gating cell insertion.
    - Added "bufnorm" experimental pass to convert design into
      buffered-normalized form.
-    - Added experimental "aiger2" and "xaiger2" backends, and an 
+    - Added experimental "aiger2" and "xaiger2" backends, and an
      experimental "abc_new" command
    - Added "-force-detailed-loop-check" option to "check" pass.
    - Added "-unit_delay" option to "read_liberty" pass.
@ -348,10 +348,10 @@ Yosys 0.43 .. Yosys 0.44
    - Build support for Haiku OS.

 * New commands and options
-    - Added "keep_hierarchy" pass to add attribute with 
+    - Added "keep_hierarchy" pass to add attribute with
      same name to modules based on cost.
    - Added options "-noopt","-bloat" and "-check_cost" to
-      "test_cell" pass. 
+      "test_cell" pass.

 * New back-ends
    - Added initial PolarFire support. ( synth_microchip )
@ -365,22 +365,22 @@ Yosys 0.42 .. Yosys 0.43

 * Verific support
    - Support building Yosys with various Verific library
-      configurations. Can be built now without YosysHQ 
+      configurations. Can be built now without YosysHQ
      specific patch and extension library.

 Yosys 0.41 .. Yosys 0.42
 --------------------------
 * New commands and options
    - Added "box_derive" pass to derive box modules.
-    - Added option "assert-mod-count" to "select" pass. 
-    - Added option "-header","-push" and "-pop" to "log" pass. 
+    - Added option "assert-mod-count" to "select" pass.
+    - Added option "-header","-push" and "-pop" to "log" pass.
 * Intel support
    - Dropped Quartus support in "synth_intel_alm" pass.

 Yosys 0.40 .. Yosys 0.41
 --------------------------
 * New commands and options
-    - Added "cellmatch" pass for picking out standard cells automatically. 
+    - Added "cellmatch" pass for picking out standard cells automatically.

 * Various
    - Extended the experimental incremental JSON API to allow arbitrary
@ -394,7 +394,7 @@ Yosys 0.40 .. Yosys 0.41
 Yosys 0.39 .. Yosys 0.40
 --------------------------
 * New commands and options
-    - Added option "-vhdl2019" to "read" and "verific" pass. 
+    - Added option "-vhdl2019" to "read" and "verific" pass.

 * Various
    - Major documentation overhaul.
@ -408,7 +408,7 @@ Yosys 0.39 .. Yosys 0.40
 Yosys 0.38 .. Yosys 0.39
 --------------------------
 * New commands and options
-    - Added option "-extra-map" to "synth" pass. 
+    - Added option "-extra-map" to "synth" pass.
    - Added option "-dont_use" to "dfflibmap" pass.
    - Added option "-href" to "show" command.
    - Added option "-noscopeinfo" to "flatten" pass.
@ -422,7 +422,7 @@ Yosys 0.38 .. Yosys 0.39
      the hierarchy during flattening.
    - Added sequential area output to "stat -liberty".
    - Added ability to record/replay diagnostics in cxxrtl backend.
- 
+
 * Verific support
    - Added attributes to module instantiation.

@ -469,7 +469,7 @@ Yosys 0.35 .. Yosys 0.36

 * QuickLogic support
    - Added "K6N10f" support.
-    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to 
+    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to
      "synth_quicklogic" pass.
    - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
    - Added "ql_bram_types" pass to change TDP36K depending on configuration.
@ -564,7 +564,7 @@ Yosys 0.29 .. Yosys 0.30
    - Added remaining primitives blackboxes.

 * Various
-    - "show -colorattr" will now color the cells, wires, and 
+    - "show -colorattr" will now color the cells, wires, and
      connection arrows.
    - "show -viewer none" will not execute viewer.

@ -739,7 +739,7 @@ Yosys 0.19 .. Yosys 0.20
      operators were not affected.

 * Verific support
-    - Proper import of port ranges into Yosys, may result in reversed 
+    - Proper import of port ranges into Yosys, may result in reversed
      bit-order of top-level ports for some synthesis flows.

 Yosys 0.18 .. Yosys 0.19
@ -833,7 +833,7 @@ Yosys 0.14 .. Yosys 0.15

 * SystemVerilog
    - Added support for accessing whole sub-structures in expressions
- 
+
 * New commands and options
    - Added glift command, used to create gate-level information flow tracking
      (GLIFT) models by the "constructive mapping" approach
@ -848,7 +848,7 @@ Yosys 0.13 .. Yosys 0.14
    - Added $bmux and $demux cells and related optimization patterns.

 * New commands and options
-    - Added "bmuxmap" and "dmuxmap" passes 
+    - Added "bmuxmap" and "dmuxmap" passes
    - Added "-fst" option to "sim" pass for writing FST files
    - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
      "-sim-gold" options to "sim" pass for co-simulation
@ -1802,4 +1802,3 @@ Yosys 0.1.0 .. Yosys 0.2.0
     - Added "design -stash/-copy-from/-copy-to"
     - Added "copy" command
     - Added "splice" command
-
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -9,7 +9,7 @@ if (CMAKE_BINARY_DIR STREQUAL CMAKE_SOURCE_DIR)
 	)
 endif()

-cmake_minimum_required(VERSION 3.27)
+cmake_minimum_required(VERSION 3.28)
 project(yosys LANGUAGES C CXX)

 set(CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake" ${CMAKE_MODULE_PATH})
@ -29,11 +29,17 @@ include(YosysLinkTarget)
 include(YosysAbc)
 include(YosysAbcSubmodule)
 include(YosysVerific)
+include(UseHomebrew)
+
+# Fix for using Clang from nixpkgs
+# see https://github.com/YosysHQ/yosys/pull/5936#issuecomment-4637319568
+set(CMAKE_CXX_SCAN_FOR_MODULES NO)

 # Build options.
 set(YOSYS_COMPILER_LAUNCHER "" CACHE STRING "Compiler launcher (ccache, sccache)")
 option(YOSYS_ENABLE_COVERAGE "Enable code coverage" OFF)
 option(YOSYS_ENABLE_PROFILING "Enable instruction profiling" OFF)
+option(YOSYS_ENABLE_FUNCTIONAL_TESTS "Enable running functional tests" OFF)

 set(YOSYS_PROGRAM_PREFIX "" CACHE STRING "Name prefix for programs, libraries, and data")
 set(YOSYS_COMPONENTS "everything" CACHE STRING "List of components to build (use pass names)")
@ -162,7 +168,12 @@ if (MINGW AND CMAKE_CXX_COMPILER_ID STREQUAL "GNU" AND CMAKE_CXX_COMPILER_VERSIO
 endif()

 # Required dependencies.
-find_package(FLEX)
+if (APPLE)
+	# In practice, we can't expect paths to Homebrew packages to be configured.
+	use_homebrew()
+endif()
+
+find_package(FLEX 2.6)
 set_package_properties(FLEX PROPERTIES
 	URL "https://github.com/westes/flex"
 	DESCRIPTION "The Fast Lexical Analyzer"
@ -170,7 +181,7 @@ set_package_properties(FLEX PROPERTIES
 	TYPE REQUIRED
 )

-find_package(BISON)
+find_package(BISON 3.6)
 set_package_properties(BISON PROPERTIES
 	URL "https://www.gnu.org/software/bison/"
 	DESCRIPTION "The Yacc-compatible Parser Generator"
@ -528,8 +539,20 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)

 	add_custom_target(test-vanilla
 		COMMAND make vanilla-test ${makefile_vars}
+			ENABLE_FUNCTIONAL_TESTS=$<IF:$<BOOL:${YOSYS_ENABLE_FUNCTIONAL_TESTS}>,1,0>
 		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests
 		DEPENDS ${makefile_depends}
+		USES_TERMINAL
+		JOB_SERVER_AWARE TRUE
+	)
+
+	add_custom_target(test-functional
+		COMMAND make functional ${makefile_vars}
+			ENABLE_FUNCTIONAL_TESTS=$<IF:$<BOOL:${YOSYS_ENABLE_FUNCTIONAL_TESTS}>,1,0>
+		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests
+		DEPENDS ${makefile_depends}
+		USES_TERMINAL
+		JOB_SERVER_AWARE TRUE
 	)

 	add_custom_target(test
@ -541,6 +564,7 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)
 		COMMAND make gen ${makefile_vars}
 		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/docs
 		DEPENDS ${makefile_depends}
+		JOB_SERVER_AWARE TRUE
 	)
 	foreach (format html latexpdf)
 		add_custom_target(docs-${format}
@ -553,6 +577,7 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY)
 		COMMAND make test ${makefile_vars}
 		WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/docs
 		DEPENDS ${makefile_depends}
+		JOB_SERVER_AWARE TRUE
 	)
 endif()

--- a/README.md
+++ b/README.md
@ -76,7 +76,7 @@ or
 	$ git submodule update --init --recursive

 A C++ compiler with C++20 support is required as well as some standard tools
-such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.27), Make (or other CMake
+such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake
 generator such as Ninja), and Python (>=3.11). Some additional tools: readline,
 libffi, Tcl and zlib; will be used if available but are optional. Graphviz and
 Xdot are used by the `show` command to display schematics.
@ -303,4 +303,3 @@ DOCS (e.g.)
 This will build/rebuild yosys as necessary before generating the website
 documentation from the yosys help commands.  To build for pdf instead of html,
 use the `docs-latexpdf` target.
-
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 8017a0347bf457aaee6a7e023de34f4b280481bc
+Subproject commit a2b0f3455f33c8d9a9da3ef4bec317519c64ec7c
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@ -95,7 +95,7 @@ struct XAigerWriter
 		}

 		bit2aig_stack.push_back(bit);
-		
+
 		// NB: Cannot use iterator returned from aig_map.insert()
 		//     since this function is called recursively

--- a/backends/btor/test_cells.sh
+++ b/backends/btor/test_cells.sh
@ -27,4 +27,3 @@ for fn in test_*.il; do
 done

 echo "OK."
-
--- a/backends/cxxrtl/runtime/README.txt
+++ b/backends/cxxrtl/runtime/README.txt
@ -15,4 +15,4 @@ file of the simulation toplevel).
 The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice.

 For clarity, all of the files in this directory and its subdirectories have unique names regardless
-of the directory where they are placed.
+of the directory where they are placed.
--- a/backends/edif/runtest.py
+++ b/backends/edif/runtest.py
@ -118,4 +118,3 @@ os.system("set -x; ./test_gold > test_gold.out")
 os.system("set -x; ./test_gate > test_gate.out")

 os.system("set -x; md5sum test_gold.out test_gate.out")
-
--- a/backends/functional/smtlib.cc
+++ b/backends/functional/smtlib.cc
@ -187,7 +187,7 @@ struct SmtModule {
 	Functional::IR ir;
 	SmtScope scope;
 	std::string name;
-	
+
 	SmtStruct input_struct;
 	SmtStruct output_struct;
 	SmtStruct state_struct;
@ -256,7 +256,7 @@ struct SmtModule {
 	}

 	void write(std::ostream &out)
-	{    
+	{
 		SExprWriter w(out);

 		input_struct.write_definition(w);
@ -266,7 +266,7 @@ struct SmtModule {
 		w << list("declare-datatypes",
 			list(list("Pair", 2)),
 			list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
-		
+
 		write_eval(w);
 		write_initial(w);
 	}
--- a/backends/functional/smtlib_rosette.cc
+++ b/backends/functional/smtlib_rosette.cc
@ -304,7 +304,7 @@ struct SmtrModule {
 	}

 	void write(std::ostream &out)
-	{    
+	{
 		SExprWriter w(out);

 		input_struct.write_definition(w);
--- a/backends/functional/test_generic.cc
+++ b/backends/functional/test_generic.cc
@ -46,7 +46,7 @@ struct MemContentsTest {
 		error:
 		printf("FAIL\n");
 		int digits = (data_width + 3) / 4;
-		
+
 		for(auto addr = 0; addr < (1<<addr_width); addr++) {
 			if(addr % 8 == 0) printf("%.8x   ", addr);
 			auto it = reference.find(addr);
--- a/backends/simplec/test00_uut.v
+++ b/backends/simplec/test00_uut.v
@ -11,4 +11,3 @@ endmodule
 module unit_y(input [31:0] a, b, c, output [31:0] y);
  assign y = a & (b | c);
 endmodule
-
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@ -788,7 +788,7 @@ struct Smt2Worker
 			if (has_async_wr && has_sync_wr)
 				log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", cell, module);

-			decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", mem->memid.unescape(), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
+			decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d %s\n", get_id(mem->memid), abits, mem->width, GetSize(mem->rd_ports), GetSize(mem->wr_ports), has_async_wr ? "async" : "sync"));
 			decls.push_back(witness_memory(get_id(mem->memid), cell, mem));

 			string memstate;
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@ -226,7 +226,7 @@ class SmtIo:
                print('timeout option is not supported for mathsat.')
                sys.exit(1)

-        if self.solver in ["boolector", "bitwuzla"]:
+        if self.solver == "boolector":
            if self.noincr:
                self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
            else:
@ -236,6 +236,29 @@ class SmtIo:
                print('timeout option is not supported for %s.' % self.solver)
                sys.exit(1)

+        if self.solver == "bitwuzla":
+            try:
+                help_text = subprocess.check_output([self.solver, "--help"], text=True)
+            except FileNotFoundError:
+                print("%s SMT Solver '%s' not found in path." % (self.timestamp(), self.solver), flush=True)
+                sys.exit(1)
+            if "--lang" in help_text:
+                self.popen_vargs = [self.solver, '--lang', 'smt2'] + self.solver_opts
+                self.unroll = True
+                if self.timeout != 0:
+                    self.popen_vargs.append('--time-limit')
+                    self.popen_vargs.append('%d000' % self.timeout)
+            else:
+                # Versions before 0.3
+                if self.noincr:
+                    self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts
+                else:
+                    self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts
+                self.unroll = True
+                if self.timeout != 0:
+                    print('timeout option is not supported for %s.' % self.solver)
+                    sys.exit(1)
+
        if self.solver == "abc":
            if len(self.solver_opts) > 0:
                self.popen_vargs = ['yosys-abc', '-S', '; '.join(self.solver_opts)]
--- a/backends/smt2/test_cells.sh
+++ b/backends/smt2/test_cells.sh
@ -52,4 +52,3 @@ echo ""
 echo "  All tests passed."
 echo ""
 exit 0
-
--- a/backends/smt2/ywio.py
+++ b/backends/smt2/ywio.py
@ -398,13 +398,13 @@ class ReadWitness:

    def init_step(self):
        return self.step(0)
-    
+
    def non_init_bits(self):
        if len(self) > 1:
            return len(self.bits[1])
        else:
            return sum([sig.width for sig in self.signals if not sig.init_only])
-    
+
    def first_step(self):
        values = WitnessValues()
        # may have issues when non_init_bits is 0
--- a/backends/smv/test_cells.sh
+++ b/backends/smv/test_cells.sh
@ -30,4 +30,3 @@ for fn in test_*.il; do
 done

 grep '^-- invariant .* is false' *.out || echo 'All OK.'
-
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@ -197,14 +197,22 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)

 	reg_name = id(chunk.wire->name);
 	if (sig.size() != chunk.wire->width) {
-		if (sig.size() == 1)
-			reg_name += stringf("[%d]", chunk.wire->start_offset +  chunk.offset);
-		else if (chunk.wire->upto)
-			reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
-					(chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
+		int idx;
+		if (chunk.wire->upto)
+			idx = (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset;
 		else
-			reg_name += stringf("[%d:%d]", chunk.wire->start_offset +  chunk.offset + chunk.width - 1,
-					chunk.wire->start_offset +  chunk.offset);
+			idx = chunk.wire->start_offset + chunk.offset;
+
+		if (sig.size() == 1)
+			reg_name += stringf("[%d]", idx);
+		else {
+			int left_idx;
+			if (chunk.wire->upto)
+				left_idx = (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset;
+			else
+				left_idx = chunk.wire->start_offset +  chunk.offset + chunk.width - 1;
+			reg_name += stringf("[%d:%d]", left_idx, idx);
+		}
 	}

 	return true;
@ -474,21 +482,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 		if (wire->attributes.count(ID::single_bit_vector))
 			range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
 	}
+	std::string sign = wire->is_signed ? " signed" : "";
 	if (wire->port_input && !wire->port_output)
-		f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (!wire->port_input && wire->port_output)
-		f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (wire->port_input && wire->port_output)
-		f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name));
 	if (reg_wires.count(wire->name)) {
-		f << stringf("%s" "reg%s %s", indent, range, id(wire->name));
+		f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name));
 		if (wire->attributes.count(ID::init)) {
 			f << stringf(" = ");
 			dump_const(f, wire->attributes.at(ID::init));
 		}
 		f << stringf(";\n");
 	} else
-		f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name));
+		f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name));
 #endif
 }

--- a/cmake/FindBISON.cmake
+++ b/cmake/FindBISON.cmake
@ -0,0 +1,346 @@
+# Based on CMake v3.31.0 `Modules/FindBISON.cmake`, changed as follows:
+# - Continue searching for Bison if an executable does not match the requested
+#   version constraint.
+# - Search for a usable M4 and run Bison with the `M4` environment variable.
+
+# Distributed under the OSI-approved BSD 3-Clause License.  See accompanying
+# file Copyright.txt or https://cmake.org/licensing for details.
+
+#[=======================================================================[.rst:
+FindBISON
+---------
+
+Find ``bison`` executable and provide a macro to generate custom build rules.
+
+The module defines the following variables:
+
+``BISON_EXECUTABLE``
+  path to the ``bison`` program
+
+``BISON_VERSION``
+  version of ``bison``
+
+``BISON_FOUND``
+  "True" if the program was found
+
+The minimum required version of ``bison`` can be specified using the
+standard CMake syntax, e.g.  :command:`find_package(BISON 2.1.3)`.
+
+If ``bison`` is found, the module defines the macro::
+
+  BISON_TARGET(<Name> <YaccInput> <CodeOutput>
+               [COMPILE_FLAGS <flags>]
+               [DEFINES_FILE <file>]
+               [VERBOSE [<file>]]
+               [REPORT_FILE <file>]
+               )
+
+which will create a custom rule to generate a parser.  ``<YaccInput>`` is
+the path to a yacc file.  ``<CodeOutput>`` is the name of the source file
+generated by bison.  A header file is also be generated, and contains
+the token list.
+
+.. versionchanged:: 3.14
+  When :policy:`CMP0088` is set to ``NEW``, ``bison`` runs in the
+  :variable:`CMAKE_CURRENT_BINARY_DIR` directory.
+
+The options are:
+
+``COMPILE_FLAGS <flags>``
+  Specify flags to be added to the ``bison`` command line.
+
+``DEFINES_FILE <file>``
+  .. versionadded:: 3.4
+
+  Specify a non-default header ``<file>`` to be generated by ``bison``.
+
+``VERBOSE [<file>]``
+  Tell ``bison`` to write a report file of the grammar and parser.
+
+  .. deprecated:: 3.7
+    If ``<file>`` is given, it specifies path the report file is copied to.
+    ``[<file>]`` is left for backward compatibility of this module.
+    Use ``VERBOSE REPORT_FILE <file>``.
+
+``REPORT_FILE <file>``
+  .. versionadded:: 3.7
+
+  Specify a non-default report ``<file>``, if generated.
+
+The macro defines the following variables:
+
+``BISON_<Name>_DEFINED``
+  ``True`` is the macro ran successfully
+
+``BISON_<Name>_INPUT``
+  The input source file, an alias for <YaccInput>
+
+``BISON_<Name>_OUTPUT_SOURCE``
+  The source file generated by bison
+
+``BISON_<Name>_OUTPUT_HEADER``
+  The header file generated by bison
+
+``BISON_<Name>_OUTPUTS``
+  All files generated by bison including the source, the header and the report
+
+``BISON_<Name>_COMPILE_FLAGS``
+  Options used in the ``bison`` command line
+
+Example usage:
+
+.. code-block:: cmake
+
+  find_package(BISON)
+  BISON_TARGET(MyParser parser.y ${CMAKE_CURRENT_BINARY_DIR}/parser.cpp
+               DEFINES_FILE ${CMAKE_CURRENT_BINARY_DIR}/parser.h)
+  add_executable(Foo main.cpp ${BISON_MyParser_OUTPUTS})
+#]=======================================================================]
+
+function(BISON_m4_validator result_var executable)
+  execute_process(COMMAND ${executable} --version
+    OUTPUT_QUIET
+    ERROR_QUIET
+    RESULT_VARIABLE M4_version_result
+	)
+	if (NOT M4_version_result EQUAL 0)
+	  set(${result_var} FALSE PARENT_SCOPE)
+	endif()
+endfunction()
+
+find_program(BISON_M4_EXECUTABLE
+  NAMES m4
+  VALIDATOR BISON_m4_validator
+  DOC "path to the m4 executable (used by bison)"
+)
+
+function(BISON_get_version result_var executable)
+  # the bison commands should be executed with the C locale, otherwise
+  # the message (which are parsed) may be translated
+  set(_Bison_SAVED_LC_ALL "$ENV{LC_ALL}")
+  set(ENV{LC_ALL} C)
+
+  execute_process(COMMAND ${executable} --version
+    OUTPUT_VARIABLE BISON_version_output
+    ERROR_VARIABLE BISON_version_error
+    RESULT_VARIABLE BISON_version_result
+    OUTPUT_STRIP_TRAILING_WHITESPACE)
+
+  set(ENV{LC_ALL} ${_Bison_SAVED_LC_ALL})
+
+  if(NOT ${BISON_version_result} EQUAL 0)
+    message(SEND_ERROR "Command \"${executable} --version\" failed with output:\n${BISON_version_error}")
+  else()
+    # Bison++
+    if("${BISON_version_output}" MATCHES "^bison\\+\\+ Version ([^,]+)")
+      set(${result_var} "${CMAKE_MATCH_1}")
+    # GNU Bison
+    elseif("${BISON_version_output}" MATCHES "^bison \\(GNU Bison\\) ([^\n]+)\n")
+      set(${result_var} "${CMAKE_MATCH_1}")
+    elseif("${BISON_version_output}" MATCHES "^GNU Bison (version )?([^\n]+)")
+      set(${result_var} "${CMAKE_MATCH_2}")
+    endif()
+  endif()
+
+  return(PROPAGATE ${result_var})
+endfunction()
+
+function(BISON_validator result_var executable)
+  BISON_get_version(bison_version ${executable})
+  find_package_check_version("${bison_version}" ${result_var})
+  return(PROPAGATE ${result_var})
+endfunction()
+
+find_program(BISON_EXECUTABLE
+  NAMES bison win-bison win_bison
+  VALIDATOR BISON_validator
+  DOC "path to the bison executable"
+)
+mark_as_advanced(BISON_EXECUTABLE)
+
+if(BISON_EXECUTABLE)
+  BISON_get_version(BISON_VERSION ${BISON_EXECUTABLE})
+
+  # internal macro
+  # sets BISON_TARGET_cmdopt
+  macro(BISON_TARGET_option_extraopts Options)
+    set(BISON_TARGET_cmdopt "")
+    set(BISON_TARGET_extraopts "${Options}")
+    separate_arguments(BISON_TARGET_extraopts)
+    list(APPEND BISON_TARGET_cmdopt ${BISON_TARGET_extraopts})
+  endmacro()
+
+  # internal macro
+  # sets BISON_TARGET_output_header and BISON_TARGET_cmdopt
+  macro(BISON_TARGET_option_defines BisonOutput Header)
+    if("${Header}" STREQUAL "")
+      # default header path generated by bison (see option -d)
+      string(REGEX REPLACE "^(.*)(\\.[^.]*)$" "\\2" _fileext "${BisonOutput}")
+      string(REPLACE "c" "h" _fileext ${_fileext})
+      string(REGEX REPLACE "^(.*)(\\.[^.]*)$" "\\1${_fileext}"
+          BISON_TARGET_output_header "${BisonOutput}")
+      list(APPEND BISON_TARGET_cmdopt "-d")
+    else()
+      set(BISON_TARGET_output_header "${Header}")
+      list(APPEND BISON_TARGET_cmdopt "--defines=${BISON_TARGET_output_header}")
+    endif()
+  endmacro()
+
+  # internal macro
+  # sets BISON_TARGET_verbose_file and BISON_TARGET_cmdopt
+  macro(BISON_TARGET_option_report_file BisonOutput ReportFile)
+    if("${ReportFile}" STREQUAL "")
+      get_filename_component(BISON_TARGET_output_path "${BisonOutput}" PATH)
+      get_filename_component(BISON_TARGET_output_name "${BisonOutput}" NAME_WE)
+      set(BISON_TARGET_verbose_file
+        "${BISON_TARGET_output_path}/${BISON_TARGET_output_name}.output")
+    else()
+      set(BISON_TARGET_verbose_file "${ReportFile}")
+      list(APPEND BISON_TARGET_cmdopt "--report-file=${BISON_TARGET_verbose_file}")
+    endif()
+    if(NOT IS_ABSOLUTE "${BISON_TARGET_verbose_file}")
+      cmake_policy(GET CMP0088 _BISON_CMP0088
+        PARENT_SCOPE # undocumented, do not use outside of CMake
+        )
+      if("x${_BISON_CMP0088}x" STREQUAL "xNEWx")
+        set(BISON_TARGET_verbose_file "${CMAKE_CURRENT_BINARY_DIR}/${BISON_TARGET_verbose_file}")
+      else()
+        set(BISON_TARGET_verbose_file "${CMAKE_CURRENT_SOURCE_DIR}/${BISON_TARGET_verbose_file}")
+      endif()
+      unset(_BISON_CMP0088)
+    endif()
+  endmacro()
+
+  # internal macro
+  # adds a custom command and sets
+  #   BISON_TARGET_cmdopt, BISON_TARGET_extraoutputs
+  macro(BISON_TARGET_option_verbose Name BisonOutput filename)
+    cmake_policy(GET CMP0088 _BISON_CMP0088
+        PARENT_SCOPE # undocumented, do not use outside of CMake
+        )
+    set(_BISON_WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
+    if("x${_BISON_CMP0088}x" STREQUAL "xNEWx")
+      set(_BISON_WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
+    endif()
+    unset(_BISON_CMP0088)
+
+    list(APPEND BISON_TARGET_cmdopt "--verbose")
+    list(APPEND BISON_TARGET_outputs
+      "${BISON_TARGET_verbose_file}")
+    if (NOT "${filename}" STREQUAL "")
+      if(IS_ABSOLUTE "${filename}")
+        set(BISON_TARGET_verbose_extra_file "${filename}")
+      else()
+        set(BISON_TARGET_verbose_extra_file "${_BISON_WORKING_DIRECTORY}/${filename}")
+      endif()
+
+      add_custom_command(OUTPUT ${BISON_TARGET_verbose_extra_file}
+        COMMAND ${CMAKE_COMMAND} -E copy
+        "${BISON_TARGET_verbose_file}"
+        "${filename}"
+        VERBATIM
+        DEPENDS
+        "${BISON_TARGET_verbose_file}"
+        COMMENT "[BISON][${Name}] Copying bison verbose table to ${filename}"
+        WORKING_DIRECTORY ${_BISON_WORKING_DIRECTORY})
+      list(APPEND BISON_TARGET_extraoutputs
+        "${BISON_TARGET_verbose_extra_file}")
+      unset(BISON_TARGET_verbose_extra_file)
+      unset(_BISON_WORKING_DIRECTORY)
+    endif()
+  endmacro()
+
+  #============================================================
+  # BISON_TARGET (public macro)
+  #============================================================
+  #
+  macro(BISON_TARGET Name BisonInput BisonOutput)
+    set(BISON_TARGET_outputs "${BisonOutput}")
+    set(BISON_TARGET_extraoutputs "")
+
+    # Parsing parameters
+    set(BISON_TARGET_PARAM_OPTIONS
+      )
+    set(BISON_TARGET_PARAM_ONE_VALUE_KEYWORDS
+      COMPILE_FLAGS
+      DEFINES_FILE
+      REPORT_FILE
+      )
+    set(BISON_TARGET_PARAM_MULTI_VALUE_KEYWORDS
+      VERBOSE
+      )
+    cmake_parse_arguments(
+        BISON_TARGET_ARG
+        "${BISON_TARGET_PARAM_OPTIONS}"
+        "${BISON_TARGET_PARAM_ONE_VALUE_KEYWORDS}"
+        "${BISON_TARGET_PARAM_MULTI_VALUE_KEYWORDS}"
+        ${ARGN}
+    )
+
+    if(NOT "${BISON_TARGET_ARG_UNPARSED_ARGUMENTS}" STREQUAL "")
+      message(SEND_ERROR "Usage")
+    elseif("${BISON_TARGET_ARG_VERBOSE}" MATCHES ";")
+      # [VERBOSE [<file>] hack: <file> is non-multi value by usage
+      message(SEND_ERROR "Usage")
+    else()
+
+      BISON_TARGET_option_extraopts("${BISON_TARGET_ARG_COMPILE_FLAGS}")
+      BISON_TARGET_option_defines("${BisonOutput}" "${BISON_TARGET_ARG_DEFINES_FILE}")
+      BISON_TARGET_option_report_file("${BisonOutput}" "${BISON_TARGET_ARG_REPORT_FILE}")
+      if(NOT "${BISON_TARGET_ARG_VERBOSE}" STREQUAL "")
+        BISON_TARGET_option_verbose(${Name} ${BisonOutput} "${BISON_TARGET_ARG_VERBOSE}")
+      else()
+        # [VERBOSE [<file>]] is used with no argument or is not used
+        set(BISON_TARGET_args "${ARGN}")
+        list(FIND BISON_TARGET_args "VERBOSE" BISON_TARGET_args_indexof_verbose)
+        if(${BISON_TARGET_args_indexof_verbose} GREATER -1)
+          # VERBOSE is used without <file>
+          BISON_TARGET_option_verbose(${Name} ${BisonOutput} "")
+        endif()
+      endif()
+
+      list(APPEND BISON_TARGET_outputs "${BISON_TARGET_output_header}")
+
+      cmake_policy(GET CMP0088 _BISON_CMP0088
+        PARENT_SCOPE # undocumented, do not use outside of CMake
+        )
+      set(_BISON_WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
+      set(_BisonInput "${BisonInput}")
+      if("x${_BISON_CMP0088}x" STREQUAL "xNEWx")
+        set(_BISON_WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR})
+        if(NOT IS_ABSOLUTE "${_BisonInput}")
+          set(_BisonInput "${CMAKE_CURRENT_SOURCE_DIR}/${_BisonInput}")
+        endif()
+      endif()
+      unset(_BISON_CMP0088)
+
+      add_custom_command(OUTPUT ${BISON_TARGET_outputs}
+        COMMAND ${CMAKE_COMMAND} -E env "M4=${BISON_M4_EXECUTABLE}"
+          ${BISON_EXECUTABLE} ${BISON_TARGET_cmdopt} -o ${BisonOutput} ${_BisonInput}
+        VERBATIM
+        DEPENDS ${_BisonInput}
+        COMMENT "[BISON][${Name}] Building parser with bison ${BISON_VERSION}"
+        WORKING_DIRECTORY ${_BISON_WORKING_DIRECTORY})
+
+      unset(_BISON_WORKING_DIRECTORY)
+
+      # define target variables
+      set(BISON_${Name}_DEFINED TRUE)
+      set(BISON_${Name}_INPUT ${_BisonInput})
+      set(BISON_${Name}_OUTPUTS ${BISON_TARGET_outputs} ${BISON_TARGET_extraoutputs})
+      set(BISON_${Name}_COMPILE_FLAGS ${BISON_TARGET_cmdopt})
+      set(BISON_${Name}_OUTPUT_SOURCE "${BisonOutput}")
+      set(BISON_${Name}_OUTPUT_HEADER "${BISON_TARGET_output_header}")
+
+      unset(_BisonInput)
+
+    endif()
+  endmacro()
+  #
+  #============================================================
+
+endif()
+
+include(FindPackageHandleStandardArgs)
+FIND_PACKAGE_HANDLE_STANDARD_ARGS(BISON REQUIRED_VARS BISON_EXECUTABLE
+                                        VERSION_VAR BISON_VERSION)
--- a/cmake/SilimateConfig.cmake
+++ b/cmake/SilimateConfig.cmake
@ -7,5 +7,17 @@ set(YOSYS_VERIFIC_DIR ${PROJECT_SOURCE_DIR}/verific)
 set(YOSYS_WITH_PYTHON ON CACHE BOOL "" FORCE)

 add_library(verific INTERFACE)
+
+# Homebrew's binutils ships libbfd but not libiberty, which backward-cpp's libbfd
+# backend links against. When binutils happens to be installed, use_homebrew()
+# puts it on the find path and backward-cpp prefers the libbfd backend, producing
+# an unsatisfiable `-liberty` at link time. Hide binutils so backward-cpp selects
+# the intended libdwarf backend (provided by the dwarfutils + libelf packages).
+if (APPLE)
+	list(FILTER CMAKE_FIND_ROOT_PATH EXCLUDE REGEX "binutils")
+	unset(LIBBFD_LIBRARY CACHE)
+	unset(LIBBFD_INCLUDE_DIR CACHE)
+endif()
+
 add_subdirectory(${PROJECT_SOURCE_DIR}/libs/backward-cpp)
 link_libraries(backward)
--- a/cmake/UseHomebrew.cmake
+++ b/cmake/UseHomebrew.cmake
@ -0,0 +1,22 @@
+# Syntax:
+#
+# 	use_homebrew([ROOT <root>])
+#
+# Includes all packages installed in `<root>` (`/opt/homebrew/Cellar` if not specified)
+# in `CMAKE_FIND_ROOT_PATH`.
+#
+function(use_homebrew)
+	cmake_parse_arguments(PARSE_ARGV 0 arg "" "ROOT" "")
+	if (NOT arg_ROOT)
+		set(arg_ROOT /opt/homebrew/Cellar)
+	endif()
+
+	file(GLOB package_roots ${arg_ROOT}/*/*) # e.g. `/opt/homebrew/Cellar/bison/3.8.2/`
+	foreach (package_root ${package_roots})
+		if (IS_DIRECTORY ${package_root})
+			list(APPEND CMAKE_FIND_ROOT_PATH ${package_root})
+		endif()
+	endforeach()
+
+	return(PROPAGATE CMAKE_FIND_ROOT_PATH)
+endfunction()
--- a/cmake/YosysAbc.cmake
+++ b/cmake/YosysAbc.cmake
@ -42,7 +42,9 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 	list(TRANSFORM all_sources PREPEND abc/)

 	# Required to get `-DABC_NAMESPACE` below to work consistently.
-	set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX)
+	if(NOT MSVC)
+		set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX)
+	endif()

 	set(main_source abc/src/base/main/main.c)
 	list(REMOVE_ITEM all_sources ${main_source})
@ -55,14 +57,22 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 	target_include_directories(${arg_LIBNAME} PRIVATE abc/src)
 	target_compile_definitions(${arg_LIBNAME} PUBLIC
 		WIN32_NO_DLL
-		ABC_NAMESPACE=abc
+		$<$<NOT:$<CXX_COMPILER_ID:MSVC>>:ABC_NAMESPACE=abc>
 		ABC_USE_STDINT_H=1
 		ABC_USE_CUDD=1
 		ABC_NO_DYNAMIC_LINKING
 		$<${YOSYS_ENABLE_THREADS}:ABC_USE_PTHREADS>
 		$<${YOSYS_ENABLE_READLINE}:ABC_USE_READLINE>
+		$<$<CXX_COMPILER_ID:MSVC>:ABC_USE_PTHREADS>
+		$<$<CXX_COMPILER_ID:MSVC>:_WINSOCKAPI_>
+		$<$<CXX_COMPILER_ID:MSVC>:HAVE_STRUCT_TIMESPEC>
 		ABC_NO_RLIMIT
 	)
+	target_compile_options(${arg_LIBNAME} PRIVATE
+		$<$<CXX_COMPILER_ID:MSVC>:/wd4576>
+		$<$<CXX_COMPILER_ID:MSVC>:/Zc:strictStrings->
+	)
+
 	target_safe_compile_options(${arg_LIBNAME} PRIVATE
 		-fpermissive
 		-fno-exceptions
@ -78,10 +88,14 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME)
 		$<${YOSYS_ENABLE_THREADS}:Threads::Threads>
 		$<${YOSYS_ENABLE_READLINE}:PkgConfig::readline>
 		$<$<BOOL:${WIN32}>:-lshlwapi>
+		$<$<CXX_COMPILER_ID:MSVC>:${CMAKE_SOURCE_DIR}/abc/lib/x64/pthreadVC2.lib>
 	)
 	set_target_properties(${arg_LIBNAME} PROPERTIES
 		YOSYS_IS_ABC ON
 	)
+	if(MSVC)
+    	install(FILES "${CMAKE_SOURCE_DIR}/abc/lib/x64/pthreadVC2.dll" DESTINATION bin)
+	endif()

 	yosys_cxx_executable(${arg_EXENAME}
 		OUTPUT_NAME ${arg_EXENAME}
--- a/cmake/YosysVerific.cmake
+++ b/cmake/YosysVerific.cmake
@ -25,6 +25,9 @@ function(get_verific_components result)
 		list(APPEND components ${component})
 	endforeach()

+	# Always remove TCL command interface
+	list(REMOVE_ITEM components commands)
+
 	set(${result} ${components})
 	return(PROPAGATE ${result})
 endfunction()
--- a/cmake/YosysVersion.cmake
+++ b/cmake/YosysVersion.cmake
@ -70,6 +70,9 @@ function(yosys_extract_version)

 	# Build YOSYS_VERSION (just the version info).
 	set(YOSYS_VERSION "${YOSYS_VERSION_MAJOR}.${YOSYS_VERSION_MINOR}")
+	if (git_branch MATCHES "^release/v.+$")
+		set(git_distance 0)
+	endif()
 	if (git_distance STREQUAL "")
 		string(APPEND YOSYS_VERSION "+post")
 	else()
@ -107,7 +110,7 @@ function(yosys_extract_version)
 		# Build YOSYS_ORIGIN_INFO (git repository origin and branch)
 		if (git_origin AND git_branch)
 			string(REGEX REPLACE "^https://|.git$" "" git_origin ${git_origin})
-			if (git_origin STREQUAL "github.com/YosysHQ/yosys" AND git_branch MATCHES "^HEAD|main|release/v.+$")
+			if (git_origin MATCHES "github\\.com[:/]YosysHQ/yosys$" AND git_branch MATCHES "^HEAD|main|release/v.+$")
 				# Nothing to highlight.
 				set(YOSYS_ORIGIN_INFO "")
 			else()
--- a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
+++ b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
@ -279,9 +279,9 @@ This document was originally published in April 2015:
   in line 13 provides a mini synthesis-script to be used to process this cell.

   .. code-block:: c
-      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
-               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a 
-         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` 
+      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled
+               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a
+         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx``
         set and booted with a custom setup routine written in ARM assembler.
      :name: sieve

--- a/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
+++ b/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format.
 Download
 ========

-This document was originally published in November 2013: 
+This document was originally published in November 2013:
 :download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`

 ..
--- a/docs/source/appendix/env_vars.rst
+++ b/docs/source/appendix/env_vars.rst
@ -29,4 +29,3 @@ Yosys environment variables
 ``YOSYS_ABORT_ON_LOG_ERROR``
   Can be used for debugging Yosys internals.  Setting it to 1 causes abort() to
   be called when Yosys terminates with an error message.
-
--- a/docs/source/appendix/primer.rst
+++ b/docs/source/appendix/primer.rst
@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax):
 	:class: width-helper invert-helper
 	:name: fig:Basics_parsetree

-	Example parse tree for the Verilog expression 
+	Example parse tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`

 The parser converts the token list to the parse tree in :numref:`Fig. %s
@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook`
 	:class: width-helper invert-helper
 	:name: fig:Basics_ast

-	Example abstract syntax tree for the Verilog expression 
+	Example abstract syntax tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`


--- a/docs/source/appendix/rtlil_text.rst
+++ b/docs/source/appendix/rtlil_text.rst
@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections.

    <module>            ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
    <module-stmt>       ::= module <id> <eol>
-    <module-body>       ::= (<param-stmt> 
+    <module-body>       ::= (<param-stmt>
                         |   <conn-stmt>
-                         |   <wire> 
-                         |   <memory> 
-                         |   <cell> 
+                         |   <wire>
+                         |   <memory>
+                         |   <cell>
                         |   <process>)*
    <param-stmt>        ::= parameter <id> <constant>? <eol>
    <constant>          ::= <value> | <integer> | <string>
@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.

 .. code:: BNF

-    <sigspec> ::= <constant> 
+    <sigspec> ::= <constant>
               |  <wire-id>
-               |  <sigspec> [ <integer> (:<integer>)? ] 
+               |  <sigspec> [ <integer> (:<integer>)? ]
               |  { <sigspec>* }

 When a ``<wire-id>`` is specified, the wire must have been previously declared.
@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires.
    <wire>          ::= <attr-stmt>* <wire-stmt>
    <wire-stmt>     ::= wire <wire-option>* <wire-id> <eol>
    <wire-id>       ::= <id>
-    <wire-option>   ::= width <integer> 
-                     |  offset <integer> 
-                     |  input <integer> 
-                     |  output <integer> 
-                     |  inout <integer> 
-                     |  upto 
+    <wire-option>   ::= width <integer>
+                     |  offset <integer>
+                     |  input <integer>
+                     |  output <integer>
+                     |  inout <integer>
+                     |  upto
                     |  signed

 Memories
@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and

    <memory>        ::= <attr-stmt>* <memory-stmt>
    <memory-stmt>   ::= memory <memory-option>* <id> <eol>
-    <memory-option> ::= width <integer> 
-                     |  size <integer> 
+    <memory-option> ::= width <integer>
+                     |  size <integer>
                     |  offset <integer>

 Cells
@ -299,9 +299,9 @@ be:
 .. code:: BNF

    <sync>          ::= <sync-stmt> <update-stmt>*
-    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol> 
+    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol>
                     |  sync global <eol>
-                     |  sync init <eol> 
+                     |  sync init <eol>
                     |  sync always <eol>
    <sync-type>     ::= low | high | posedge | negedge | edge
    <update-stmt>   ::= update <dest-sigspec> <src-sigspec> <eol>
--- a/docs/source/cell/word_logic.rst
+++ b/docs/source/cell/word_logic.rst
@ -29,7 +29,7 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2.
    ~A[1]---+||
     A[1]--+|||
    ~A[0]-+||||
-     A[0]+||||| 
+     A[0]+|||||
         |||||| product formula
         010000 ~\A[0]
         001001 \A[1]~\A[2]
@ -43,4 +43,4 @@ values.
 .. autocellgroup:: logic
   :members:
   :source:
-   :linenos:
+   :linenos:
--- a/docs/source/cmd/index_internal.rst
+++ b/docs/source/cmd/index_internal.rst
@ -88,7 +88,7 @@ Dumping command help to json
      by ``Pass::experimental()``)
    * also title (``short_help`` argument in ``Pass::Pass``), group, and class
      name
-   
+
  + dictionary of group name to list of commands in that group

 - used by sphinx autodoc to generate help content
@ -106,7 +106,7 @@ Dumping command help to json
   code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`).  The caveat
   here is that if the ``script()`` calls ``run()`` on any commands *prior* to
   the first ``check_label`` then the auto detection will break and revert to
-   unformatted code (e.g. `synth_fabulous`). 
+   unformatted code (e.g. `synth_fabulous`).

 Command line rendering
 ~~~~~~~~~~~~~~~~~~~~~~
@ -114,7 +114,7 @@ Command line rendering
 - if ``Pass::formatted_help()`` returns true, will call
  ``PrettyHelp::log_help()``

-  + traverse over the children of the root node and render as plain text 
+  + traverse over the children of the root node and render as plain text
  + effectively the reverse of converting unformatted ``Pass::help()`` text
  + lines are broken at 80 characters while maintaining indentation (controlled
    by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`)
--- a/docs/source/code_examples/fifo/Makefile
+++ b/docs/source/code_examples/fifo/Makefile
@ -2,7 +2,7 @@ include ../../../common.mk

 DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
 DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
-MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates 
+MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
 MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells

 DOTS := $(addsuffix .dot,$(DOT_NAMES))
--- a/docs/source/code_examples/fifo/fifo.v
+++ b/docs/source/code_examples/fifo/fifo.v
@ -1,5 +1,5 @@
 // address generator/counter
-module addr_gen 
+module addr_gen
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input en, clk, rst,
@ -21,7 +21,7 @@ module addr_gen
 endmodule //addr_gen

 // Define our top level fifo entity
-module fifo 
+module fifo
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input wen, ren, clk, rst,
--- a/docs/source/code_examples/fifo/fifo.ys
+++ b/docs/source/code_examples/fifo/fifo.ys
@ -2,7 +2,7 @@
 # throw in some extra text to match what we expect if we were opening an
 # interactive terminal
 log $ yosys fifo.v
-log 
+log
 log -- Parsing `fifo.v' using frontend ` -vlog2k' --
 read_verilog -defer fifo.v

--- a/docs/source/code_examples/intro/mycells.v
+++ b/docs/source/code_examples/intro/mycells.v
@ -20,4 +20,3 @@ output reg Q;
 always @(posedge C)
 	Q <= D;
 endmodule
-
--- a/docs/source/code_examples/macc/Makefile
+++ b/docs/source/code_examples/macc/Makefile
@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 .PHONY: clean
 clean:
 	@rm -f *.dot
-
--- a/docs/source/code_examples/macc/macc_xilinx_test.ys
+++ b/docs/source/code_examples/macc/macc_xilinx_test.ys
@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2

 design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format dot -notitle
-
--- a/docs/source/code_examples/macro_commands/synth_ice40.ys
+++ b/docs/source/code_examples/macro_commands/synth_ice40.ys
@ -54,7 +54,7 @@ map_gates:
    ice40_wrapcarry
    techmap
    opt -fast
-    abc -dff -D 1 
+    abc -dff -D 1
    ice40_opt

 map_ffs:
@ -88,4 +88,3 @@ check:
    stat
    check -noinit
    blackbox =A:whitebox
-        
--- a/docs/source/code_examples/opt/opt_expr.ys
+++ b/docs/source/code_examples/opt/opt_expr.ys
@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
    input a,
    output y, z
-);  
+);
    assign y = a == a;
    assign z = a != a;
 endmodule
--- a/docs/source/code_examples/opt/opt_merge.ys
+++ b/docs/source/code_examples/opt/opt_merge.ys
@ -15,4 +15,3 @@ opt_merge after
 clean

 show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
-
--- a/docs/source/code_examples/opt/opt_muxtree.ys
+++ b/docs/source/code_examples/opt/opt_muxtree.ys
@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
    input a, b, c, d,
    output y
-);  
+);
    assign y = a ? (a ? b : c) : d;
 endmodule

@ -14,4 +14,3 @@ opt_muxtree after
 clean

 show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
-
--- a/docs/source/code_examples/scrambler/scrambler.ys
+++ b/docs/source/code_examples/scrambler/scrambler.ys
@ -19,4 +19,3 @@ eval -set in 1 -show out
 eval -set in 270369 -show out

 sat -set out 632435482
-
--- a/docs/source/code_examples/show/cmos.ys
+++ b/docs/source/code_examples/show/cmos.ys
@ -2,7 +2,7 @@
 read_verilog cmos.v
 prep -top cmos_demo
 techmap
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -format dot -prefix cmos_00

 # reset
@ -13,5 +13,5 @@ read_verilog cmos.v
 prep -top cmos_demo
 techmap
 splitnets -ports
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -lib ../intro/mycells.v -format dot -prefix cmos_01
--- a/docs/source/code_examples/synth_flow/Makefile
+++ b/docs/source/code_examples/synth_flow/Makefile
@ -17,4 +17,3 @@ examples:
 .PHONY: clean
 clean:
 	@rm -f *.dot
-
--- a/docs/source/getting_started/example_synth.rst
+++ b/docs/source/getting_started/example_synth.rst
@ -199,7 +199,7 @@ opt_expr <adv_opt_expr>`.
 .. todo:: consider a brief glossary for terms like adff

 .. seealso:: Advanced usage docs for
-   
+
   - :doc:`/using_yosys/synthesis/proc`
   - :doc:`/using_yosys/synthesis/opt`

@ -321,7 +321,7 @@ and merged with the ``raddr`` wire feeding into the `$memrd` cell.  This wire
 merging happened during the call to `clean` which we can see in the
 :ref:`flat_clean`.

-.. note:: 
+.. note::

   `flatten` and `clean` would normally be combined into a
   single :yoterm:`yosys> flatten;;` output, but they appear separately here as
@ -394,7 +394,7 @@ highlighted below:
   ``rdata`` output after `opt_dff`

 .. seealso:: Advanced usage docs for
-   
+
   - :doc:`/using_yosys/synthesis/fsm`
   - :doc:`/using_yosys/synthesis/opt`

@ -461,7 +461,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
 ``SRST=1'0``) inputs.

 .. seealso:: Advanced usage docs for
-   
+
   - :doc:`/using_yosys/synthesis/opt`
   - :doc:`/using_yosys/synthesis/techmap_synth`
   - :doc:`/using_yosys/synthesis/memory`
@ -659,7 +659,7 @@ into flip flops (the ``logic fallback``) with `memory_map`.
   complex.

 .. seealso:: Advanced usage docs for
-   
+
   - :doc:`/using_yosys/synthesis/techmap_synth`
   - :doc:`/using_yosys/synthesis/memory`

@ -757,7 +757,7 @@ cells.
   ``rdata`` output after :ref:`map_cells`

 .. seealso:: Advanced usage docs for
-   
+
   - :doc:`/using_yosys/synthesis/techmap_synth`
   - :doc:`/using_yosys/synthesis/abc`

--- a/docs/source/getting_started/installation.rst
+++ b/docs/source/getting_started/installation.rst
@ -88,7 +88,7 @@ Build prerequisites
 ^^^^^^^^^^^^^^^^^^^

 A C++ compiler with C++20 support is required as well as some standard tools
-such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.27), Make (or other CMake
+such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake
 generator such as Ninja), and Python (>=3.11). Some additional tools: readline,
 libffi, Tcl and zlib; will be used if available but are optional. Graphviz and
 Xdot are used by the `show` command to display schematics.
@ -152,7 +152,7 @@ Installing all prerequisites:
      recommended to use Windows Subsystem for Linux (WSL) and follow the
      instructions for Ubuntu.

-.. 
+..
   tab:: MSYS2 (MINGW64)

   .. code:: console
--- a/docs/source/getting_started/scripting_intro.rst
+++ b/docs/source/getting_started/scripting_intro.rst
@ -149,11 +149,11 @@ represent, see :ref:`interactive_show` and the

   Calling :yoscrypt:`show addr_gen` after `hierarchy`

-.. note:: 
+.. note::

   The `show` command requires a working installation of `GraphViz`_ and `xdot`_
   for displaying the actual circuit diagrams.
-   
+
 .. _GraphViz: http://www.graphviz.org/
 .. _xdot: https://github.com/jrfonseca/xdot.py

--- a/docs/source/introduction.rst
+++ b/docs/source/introduction.rst
@ -125,7 +125,7 @@ The first version of the Yosys documentation was published as a bachelor thesis
 at the Vienna University of Technology :cite:p:`BACC`.

 :Abstract:
-	Most of today's digital design is done in HDL code (mostly Verilog or 
+	Most of today's digital design is done in HDL code (mostly Verilog or
 	VHDL) and with the help of HDL synthesis tools.

 	In special cases such as synthesis for coarse-grain cell libraries or
@ -164,14 +164,14 @@ for specialised tasks.
 Benefits of open source HDL synthesis
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Cost (also applies to ``free as in free beer`` solutions): 
-  
+- Cost (also applies to ``free as in free beer`` solutions):
+
  Today the cost for a mask set in 180nm technology is far less than the cost
  for the design tools needed to design the mask layouts. Open Source ASIC flows
  are an important enabler for ASIC-level Open Source Hardware.

- Availability and Reproducibility: 
-  
+- Availability and Reproducibility:
+
  If you are a researcher who is publishing, you want to use tools that everyone
  else can also use. Even if most universities have access to all major
  commercial tools, you usually do not have easy access to the version that was
@ -179,14 +179,14 @@ Benefits of open source HDL synthesis
  can even release the source code of the tool you have used alongside your
  data.

- Framework: 
-  
+- Framework:
+
  Yosys is not only a tool. It is a framework that can be used as basis for
  other developments, so researchers and hackers alike do not need to re-invent
  the basic functionality. Extensibility was one of Yosys' design goals.

- All-in-one: 
-  
+- All-in-one:
+
  Because of the framework characteristics of Yosys, an increasing number of
  features become available in one tool. Yosys not only can be used for circuit
  synthesis but also for formal equivalence checking, SAT solving, and for
@ -194,8 +194,8 @@ Benefits of open source HDL synthesis
  proprietary software one needs to learn a new tool for each of these
  applications.

- Educational Tool: 
-  
+- Educational Tool:
+
  Proprietary synthesis tools are at times very secretive about their inner
  workings. They often are ``black boxes``. Yosys is very open about its
  internals and it is easy to observe the different steps of synthesis.
--- a/docs/source/literature.bib
+++ b/docs/source/literature.bib
@ -66,24 +66,24 @@
 	year = {1996}
 }

-@ARTICLE{Verilog2005, 
+@ARTICLE{Verilog2005,
 	journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
-	title={IEEE Standard for Verilog Hardware Description Language}, 
+	title={IEEE Standard for Verilog Hardware Description Language},
 	author={IEEE Standards Association and others},
-	year={2006}, 
+	year={2006},
 	doi={10.1109/IEEESTD.2006.99495}
 }

-@ARTICLE{VerilogSynth, 
+@ARTICLE{VerilogSynth,
 	journal={IEEE Std 1364.1-2002},
-	title={IEEE Standard for Verilog Register Transfer Level Synthesis}, 
+	title={IEEE Standard for Verilog Register Transfer Level Synthesis},
 	author={IEEE Standards Association and others},
-	year={2002}, 
+	year={2002},
 	doi={10.1109/IEEESTD.2002.94220}
 }

@ARTICLE{VHDL,
-	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, 
+	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)},
 	title={IEEE Standard VHDL Language Reference Manual},
 	author={IEEE Standards Association and others},
 	year={2009},
@ -92,20 +92,20 @@
 }

@ARTICLE{VHDLSynth,
-	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, 
+	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)},
 	title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
 	author={IEEE Standards Association and others},
 	year={2004},
 	doi={10.1109/IEEESTD.2004.94802}
 }

-@ARTICLE{IP-XACT, 
-	journal={IEEE Std 1685-2009}, 
-	title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, 
+@ARTICLE{IP-XACT,
+	journal={IEEE Std 1685-2009},
+	title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
 	author={IEEE Standards Association and others},
-	year={2010}, 
-	pages={C1-360}, 
-	keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, 
+	year={2010},
+	pages={C1-360},
+	keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
 	doi={10.1109/IEEESTD.2010.5417309}
 }

@ -116,7 +116,7 @@
 	isbn = {0-201-10088-6},
 	publisher = {Addison-Wesley Longman Publishing Co., Inc.},
 	address = {Boston, MA, USA}
-} 
+}

@INPROCEEDINGS{Cummings00,
 	author = {Clifford E. Cummings and Sunburst Design Inc},
@ -132,26 +132,26 @@
 	year={August 1967}
 }

-@INPROCEEDINGS{fsmextract, 
-	author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, 
-	booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, 
-	title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, 
-	year={2010}, 
-	pages={2610-2613}, 
-	keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 
+@INPROCEEDINGS{fsmextract,
+	author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
+	booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
+	title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
+	year={2010},
+	pages={2610-2613},
+	keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
 	doi={10.1109/ISCAS.2010.5537093},
 }

-@ARTICLE{MultiLevelLogicSynth, 
-	author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, 
-	journal={Proceedings of the IEEE}, 
-	title={Multilevel logic synthesis}, 
-	year={1990}, 
-	volume={78}, 
-	number={2}, 
-	pages={264-300}, 
-	keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, 
-	doi={10.1109/5.52213}, 
+@ARTICLE{MultiLevelLogicSynth,
+	author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
+	journal={Proceedings of the IEEE},
+	title={Multilevel logic synthesis},
+	year={1990},
+	volume={78},
+	number={2},
+	pages={264-300},
+	keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
+	doi={10.1109/5.52213},
 	ISSN={0018-9219},
 }

@ -171,7 +171,7 @@
 	acmid = {321925},
 	publisher = {ACM},
 	address = {New York, NY, USA},
-} 
+}

@article{een2003temporal,
  title={Temporal induction by incremental SAT solving},
--- a/docs/source/using_yosys/more_scripting/data_flow_tracking.rst
+++ b/docs/source/using_yosys/more_scripting/data_flow_tracking.rst
@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other
 input is either 1 or carries a tag of the same group. So if one input is ``0,
 "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a",
 "key:b"``, rather than simply ``0``. Note that if we add an unrelated
-``"overflow"`` tag to the first input, it would still not be propagated.
+``"overflow"`` tag to the first input, it would still not be propagated.
--- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst
+++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@ -56,7 +56,7 @@ is shown.

 .. figure:: /_images/code_examples/show/example_first.*
   :class: width-helper invert-helper
-   
+
   Output of the first `show` command in :numref:`example_ys`

 The first output shows the design directly after being read by the Verilog
@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram:

 .. figure:: /_images/code_examples/show/example_second.*
   :class: width-helper invert-helper
-   
+
   Output of the second `show` command in :numref:`example_ys`

 The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling
 `show`.

 In this script we directly call `opt` as the next step, which finally leads us
-to the third diagram: 
+to the third diagram:

 .. figure:: /_images/code_examples/show/example_third.*
   :class: width-helper invert-helper
   :name: example_out
-   
+
   Output of the third `show` command in :ref:`example_ys`
-   
+
 Here we see that the `opt` command not only has removed the artifacts left
 behind by `proc`, but also determined correctly that it can remove the first
 `$mux` cell without changing the behavior of the circuit.
@ -167,7 +167,7 @@ mapped to a cell library:
   :class: width-helper invert-helper
   :name: first_pitfall

-   A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
+   A half-adder built from simple CMOS gates, demonstrating common pitfalls when
   using `show`

 .. literalinclude:: /code_examples/show/cmos.ys
@ -176,7 +176,7 @@ mapped to a cell library:
   :end-at: cmos_00
   :name: pitfall_code
   :caption: Generating :numref:`first_pitfall`
-   
+
 First, Yosys did not have access to the cell library when this diagram was
 generated, resulting in all cell ports defaulting to being inputs. This is why
 all ports are drawn on the left side the cells are awkwardly arranged in a large
@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain
 version of the circuit before `techmap` than the gate-level circuit after
 `techmap`.

-.. Note:: 
+.. Note::

   It is generally recommended to verify the internal state of a design by
   writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
@ -327,7 +327,7 @@ tools).
 - :cmd:title:`dump`.
 - :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
  a design dynamically.
-  
+
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.

@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:

 .. figure:: /_images/code_examples/selections/memdemo_00.*
   :class: width-helper invert-helper
-   
+
   ``memdemo``

 Because this produces a rather large circuit, it can be useful to split it into
@ -459,18 +459,18 @@ below.

 .. figure:: /_images/code_examples/selections/submod_02.*
   :class: width-helper invert-helper
-   
+
   ``outstage``

 .. figure:: /_images/code_examples/selections/submod_03.*
   :class: width-helper invert-helper
   :name: selstage
-   
+
   ``selstage``

 .. figure:: /_images/code_examples/selections/submod_01.*
   :class: width-helper invert-helper
-   
+
   ``scramble``

 Evaluation of combinatorial circuits
@ -541,9 +541,9 @@ to solve this kind of problems.

 .. _MiniSAT: http://minisat.se/

-.. note:: 
-    
-    While it is possible to perform model checking directly in Yosys, it 
+.. note::
+
+    While it is possible to perform model checking directly in Yosys, it
    is highly recommended to use SBY or EQY for formal hardware verification.

 The `sat` command works very similar to the `eval` command. The main difference
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@ -81,7 +81,7 @@ Yosys frontends
   'Frontend' here means that the command is implemented as a sub-class of
   ``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``.

-.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under 
+.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under
          :doc:`/yosys_internals/extending_yosys/index`

 The `read_verilog` command
--- a/docs/source/using_yosys/more_scripting/selections.rst
+++ b/docs/source/using_yosys/more_scripting/selections.rst
@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
 If no `select` command has been made, then the "current selection" will be the
 whole design.

-.. note:: Many of the examples on this page make use of the `show` 
-   command to visually demonstrate the effect of selections.  For a more 
+.. note:: Many of the examples on this page make use of the `show`
+   command to visually demonstrate the effect of selections.  For a more
   detailed look at this command, refer to :ref:`interactive_show`.

 How to make a selection
@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated
 and pushed separately on a stack. After all arguments have been processed it
 simply creates the union of all elements on the stack. So :yoscrypt:`select
 t:$add a:foo` will select all `$add` cells and all objects with the ``foo``
-attribute set:   
+attribute set:

 .. literalinclude:: /code_examples/selections/foobaraddsub.v
   :caption: Test module for operations on selections
@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set:

 .. code-block::
   :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
-   
+
   yosys> select t:$add a:foo %i -list
   foobaraddsub/$add$foobaraddsub.v:4$1

@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
 .. figure:: /_images/code_examples/selections/memdemo_00.*
   :class: width-helper invert-helper
   :name: memdemo_00
-   
+
   Complete circuit diagram for the design shown in :numref:`memdemo_src`

 There's a lot going on there, but maybe we are only interested in the tree of
@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`:
 .. figure:: /_images/code_examples/selections/memdemo_01.*
   :class: width-helper invert-helper
   :name: memdemo_01
-   
+
   Output of :yoscrypt:`show y %ci2`

 From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is
@ -305,7 +305,7 @@ start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
 .. figure:: /_images/code_examples/selections/memdemo_02.*
   :class: width-helper invert-helper
   :name: memdemo_02
-   
+
   Output of :yoscrypt:`show y %ci5`

 That's starting to get a bit messy, so maybe we want to ignore the mux select
@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`:
 .. figure:: /_images/code_examples/selections/memdemo_03.*
   :class: width-helper invert-helper
   :name: memdemo_03
-   
+
   Output of :yoscrypt:`show y %ci5:-$mux[S]`

 We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells:
 .. figure:: /_images/code_examples/selections/memdemo_05.*
   :class: width-helper invert-helper
   :name: memdemo_05
-   
+
   Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``

 Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``:
 .. figure:: /_images/code_examples/selections/memdemo_04.*
   :class: width-helper invert-helper
   :name: memdemo_04
-   
+
   Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`

 Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts
--- a/docs/source/using_yosys/synthesis/abc.rst
+++ b/docs/source/using_yosys/synthesis/abc.rst
@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
 critical path, while the generally-longer paths result in ABC9 being able to
 reduce design area by mapping other logic to slower cells with greater logic
 density.
-
--- a/docs/source/using_yosys/synthesis/cell_libs.rst
+++ b/docs/source/using_yosys/synthesis/cell_libs.rst
@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document.
   The :file:`counter.ys` script includes the commands used to generate the
   images in this document.  Code snippets in this document skip these commands;
   including line numbers to allow the reader to follow along with the source.
-   
+
   To learn more about these commands, check out :ref:`interactive_show`.

 .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
@ -37,7 +37,7 @@ First, let's quickly look at the design:
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
 ``en``, is high then the ``count`` register will increment by 1 each rising edge
-of the clock, ``clk``.  
+of the clock, ``clk``.

 Loading the design
 ~~~~~~~~~~~~~~~~~~
--- a/docs/source/using_yosys/synthesis/extract.rst
+++ b/docs/source/using_yosys/synthesis/extract.rst
@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_.

 .. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
    :class: width-helper invert-helper
-    
+
    before `extract`

 .. literalinclude:: /code_examples/macc/macc_simple_test.ys
@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_.

 .. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
    :class: width-helper invert-helper
-    
+
    after `extract`

 .. literalinclude:: /code_examples/macc/macc_simple_test.v
@ -228,4 +228,4 @@ Unwrap in ``test2``:
    :end-before: end part e

 .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
-    :class: width-helper invert-helper
+    :class: width-helper invert-helper
--- a/docs/source/using_yosys/synthesis/fsm.rst
+++ b/docs/source/using_yosys/synthesis/fsm.rst
@ -92,7 +92,7 @@ transition table. For each state:
 3. Set the state signal to the current state
 4. Try to evaluate the next state and control output
 5. If step 4 was not successful:
-   
+
   -  Recursively goto step 4 with the offending stop-signal set to 0.
   -  Recursively goto step 4 with the offending stop-signal set to 1.

--- a/docs/source/using_yosys/synthesis/index.rst
+++ b/docs/source/using_yosys/synthesis/index.rst
@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
   extract
   abc
   cell_libs
-
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@ -122,7 +122,7 @@ to four memory primitive classes available for selection:
  - Can handle arbitrary number and kind of read ports

 - LUT RAM (aka distributed RAM): uses LUT storage as RAM
-  
+
  - Supported on most FPGAs (with notable exception of ice40)
  - Usually has one synchronous write port, one or more asynchronous read ports
  - Small
@ -141,7 +141,7 @@ to four memory primitive classes available for selection:
 - Huge RAM:

  - Only supported on several targets:
-    
+
    - Some Xilinx UltraScale devices (UltraRAM)

      - Two ports, both with mutually exclusive synchronous read and write
@ -154,7 +154,7 @@ to four memory primitive classes available for selection:
      - Does not support initial data

    - Nexus (large RAM)
-      
+
      - Two ports, both with mutually exclusive synchronous read and write
      - Single clock

@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior

 		if (read_enable) begin
 			read_data <= mem[read_addr];
-		
+
 		if (write_enable && read_addr == write_addr)
 			// this if block
 			read_data <= 'x;
@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior
 		if (write_enable)
 			mem[write_addr] <= write_data;

-		if (read_enable) 
+		if (read_enable)
 			read_data <= mem[read_addr];
 	end

@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior
 		if (read_enable)
 			if (write_enable)
 				read_data <= write_data;
-			else 
+			else
 				read_data <= mem[addr];
 	end

@ -787,4 +787,3 @@ Asynchronous writes
 	end

 	assign read_data = mem[read_addr];
-
--- a/docs/source/using_yosys/synthesis/techmap_synth.rst
+++ b/docs/source/using_yosys/synthesis/techmap_synth.rst
@ -1,4 +1,4 @@
-Technology mapping 
+Technology mapping
 ==================

 .. todo:: less academic, check text is coherent
--- a/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst
+++ b/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst
@ -240,7 +240,7 @@ the design at each log header.

 A worked example
 ~~~~~~~~~~~~~~~~
-  
+
 Say you did all the minimization and found that an error in `synth_xilinx`
 occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with
 ``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``.
--- a/docs/source/yosys_internals/extending_yosys/extensions.rst
+++ b/docs/source/yosys_internals/extending_yosys/extensions.rst
@ -68,7 +68,7 @@ with, and lists off the current design's modules.
   :language: c++
   :lines: 1, 4, 6, 7-20
   :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc`
-   
+
 Note that we are making a global instance of a class derived from
 ``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`.

--- a/docs/source/yosys_internals/extending_yosys/index.rst
+++ b/docs/source/yosys_internals/extending_yosys/index.rst
@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds.
   advanced_bugpoint
   contributing
   test_suites
-
--- a/docs/source/yosys_internals/extending_yosys/test_suites.rst
+++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst
@ -16,6 +16,20 @@ tests.
   cmake -B build .
   cmake --build build --target test --parallel $(nproc)

+.. warning::
+
+   There are limitations when using `Ninja` as generator, so we suggest using
+   `Unix Makefiles` to make running tests in parallel possible. However, it is
+   possible to use it directly by running:
+
+.. code:: console
+
+   cd tests
+   make -j9
+
+Please note that in this case default build directory is `build` but can be
+overwritten by providing `BUILD_DIR` variable.
+
 Vanilla tests
 ~~~~~~~~~~~~~

@ -76,15 +90,19 @@ If you don't have one of the :ref:`getting_started/installation:CAD suite(s)`
 installed, you should also install Z3 `following their
 instructions <https://github.com/Z3Prover/z3>`_.

-.. TODO:: CMAKE_TODO
+Functional tests are disabled by default, to enable them use next code snippet
+and run tests as usual:

-   How does this work under CMake?  Is it only via ``make -C tests
-   ENABLE_FUNCTIONAL_TESTS=1`` and then manually setting ``BUILD_DIR`` and
-   ``PROGRAM_PREFIX``?  And possibly also setting ``YOSYS`` et al if there is a
-   ``.exe``.  Previous instructions:
+.. code:: console

-   Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling
-   ``make test`` and the functional tests will be run as well.
+   cmake -B build . -DYOSYS_ENABLE_FUNCTIONAL_TESTS=ON
+   cmake --build build --target test --parallel $(nproc)
+
+Or run just functional tests with:
+
+.. code:: console
+
+   cmake --build build --target test-functional

 Docs tests
 ~~~~~~~~~~
@ -164,6 +182,9 @@ compiler versions.  For up to date information, including OS versions, refer to
   test for ``kernel/celledges.cc``, you will need to create a file like this:
   ``tests/unit/kernel/celledgesTest.cc``;
   * Implement your unit test
+   * Add unit test to file list in `CMakeLists.txt`
+   In case unit tests are added to new directory, note that you need also to
+   create new `CmakeList.txt` file and add ``yosys_gtest(dir-name unit-test.cc)```

   Run unit tests
   ~~~~~~~~~~~~~~
@ -172,10 +193,4 @@ compiler versions.  For up to date information, including OS versions, refer to

   .. code-block:: console

-      make unit-test
-
-   If you want to remove all unit test files, type:
-
-   .. code-block:: console
-
-      make clean-unit-test
+      cmake --build build --target test-unit
--- a/docs/source/yosys_internals/flow/index.rst
+++ b/docs/source/yosys_internals/flow/index.rst
@ -10,10 +10,9 @@ These scripts contain three types of commands:
 - **Backends**, that write the design in memory to a file (various formats are
  available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).

-.. toctree:: 
+.. toctree::
 	:maxdepth: 3

 	overview
 	control_and_data
 	verilog_frontend
-
--- a/docs/source/yosys_internals/flow/verilog_frontend.rst
+++ b/docs/source/yosys_internals/flow/verilog_frontend.rst
@ -432,12 +432,12 @@ variables:
    initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are
    empty.

-  | ``subst_lvalue_from`` and ``subst_lvalue_to`` 
+-  | ``subst_lvalue_from`` and ``subst_lvalue_to``
   | These two variables contain the mapping from left-hand-side signals (``\
     <name>``) to the current temporary signal for the same thing (initially
     ``$0\ <name>``).

-  | ``current_case`` 
+-  | ``current_case``
   | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case
     of the generated ``RTLIL::Process``.

@ -603,13 +603,13 @@ behavioural model in ``RTLIL::Process`` representation. The actual conversion
 from a behavioural model to an RTL representation is performed by the `proc`
 pass and the passes it launches:

-  | `proc_clean` and `proc_rmdead` 
+-  | `proc_clean` and `proc_rmdead`
   | These two passes just clean up the ``RTLIL::Process`` structure. The
     `proc_clean` pass removes empty parts (eg. empty assignments) from the
     process and `proc_rmdead` detects and removes unreachable branches from the
     process's decision trees.

-  | `proc_arst` 
+-  | `proc_arst`
   | This pass detects processes that describe d-type flip-flops with
     asynchronous resets and rewrites the process to better reflect what they
     are modelling: Before this pass, an asynchronous reset has two
@ -617,7 +617,7 @@ pass and the passes it launches:
     reset path. After this pass the sync rule for the reset is level-sensitive
     and the top-level ``RTLIL::SwitchRule`` has been removed.

-  | `proc_mux` 
+-  | `proc_mux`
   | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to
     a tree of multiplexers per written signal. After this, the
     ``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that
--- a/docs/source/yosys_internals/formats/index.rst
+++ b/docs/source/yosys_internals/formats/index.rst
@ -48,7 +48,7 @@ RTLIL and fail to run when unsupported high-level constructs are used. In such
 cases a pass that transforms the higher-level constructs to lower-level
 constructs must be called from the synthesis script first.

-.. toctree:: 
+.. toctree::
   :maxdepth: 3

   rtlil_rep
@ -56,4 +56,3 @@ constructs must be called from the synthesis script first.
 .. [1]
   In Yosys the term pass is only used to refer to commands that operate on the
   RTLIL data structure.
-
--- a/docs/source/yosys_internals/formats/rtlil_rep.rst
+++ b/docs/source/yosys_internals/formats/rtlil_rep.rst
@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties:
 -  The wire name
 -  A list of attributes
 -  A width (buses are just wires with a width more than 1)
-  Bus direction (MSB to LSB or vice versa)
-  Lowest valid bit index (LSB or MSB depending on bus direction)
+-  Bus direction (MSb to LSb or vice versa)
+-  Lowest valid bit index (LSb or MSb depending on bus direction)
 -  If the wire is a port: port number and direction (input/output/inout)

 As with modules, the attributes can be Verilog attributes imported by the
@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be
 used for coarse grain synthesis where the cells of the target architecture
 operate on entire signal vectors instead of single bit wires.

-In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
-the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
+In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either
+the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb;
 however, information from the HDL frontend is preserved so that the bus will be
 correctly indexed in error messages, backend output, constraint files, etc.

--- a/docs/tests/macro_commands.py
+++ b/docs/tests/macro_commands.py
@ -94,7 +94,7 @@ for macro in MACRO_SOURCE.glob("*.ys"):
            if expected_dict[key] and expected_dict[key] != actual_dict[key]:
                does_match = False

-        # raise error on mismatch        
+        # raise error on mismatch
        if not does_match:
            logging.error(f"Expected {expected!r}, got {actual!r}")
            raise_error = True
--- a/docs/util/RtlilLexer.py
+++ b/docs/util/RtlilLexer.py
@ -9,7 +9,7 @@ class RtlilLexer(RegexLexer):
    filenames = ['*.il']

    keyword_re = r'(always|assign|attribute|autoidx|case|cell|connect|edge|end|global|high|init|inout|input|low|memory|module|negedge|offset|output|parameter|posedge|process|real|signed|size|switch|sync|update|upto|width|wire)'
-    
+
    tokens = {
        'common': [
            (r'\s+', Whitespace),
--- a/docs/util/cell_documenter.py
+++ b/docs/util/cell_documenter.py
@ -34,7 +34,7 @@ class YosysCell:
    inputs: list[str]
    outputs: list[str]
    properties: list[str]
-    
+
 class YosysCellGroupDocumenter(Documenter):
    objtype = 'cellgroup'
    priority = 10
@ -67,7 +67,7 @@ class YosysCellGroupDocumenter(Documenter):
                for (name, obj) in cells_obj.get(self.lib_key, {}).items():
                    self.__cell_lib[name] = obj
        return self.__cell_lib
-    
+
    @classmethod
    def can_document_member(
        cls,
@ -83,7 +83,7 @@ class YosysCellGroupDocumenter(Documenter):
            self.content_indent = ''
        self.fullname = self.modname = self.name
        return True
-    
+
    def import_object(self, raiseerror: bool = False) -> bool:
        # get cell
        try:
@ -95,16 +95,16 @@ class YosysCellGroupDocumenter(Documenter):

        self.real_modname = self.modname
        return True
-    
+
    def get_sourcename(self) -> str:
        return self.env.doc2path(self.env.docname)
-    
+
    def format_name(self) -> str:
        return self.options.caption or ''

    def format_signature(self, **kwargs: Any) -> str:
        return self.modname
-    
+
    def add_directive_header(self, sig: str) -> None:
        domain = getattr(self, 'domain', 'cell')
        directive = getattr(self, 'directivetype', 'group')
@ -118,7 +118,7 @@ class YosysCellGroupDocumenter(Documenter):

        if self.options.noindex:
            self.add_line('   :noindex:', sourcename)
-    
+
    def add_content(self, more_content: Any | None) -> None:
        # groups have no native content
        # add additional content (e.g. from document), if present
@ -271,22 +271,22 @@ class YosysCellDocumenter(YosysCellGroupDocumenter):
        self.fullname = ((self.modname) + (thing or ''))

        return True
-    
+
    def import_object(self, raiseerror: bool = False) -> bool:
        if super().import_object(raiseerror):
            self.object = YosysCell(self.modname, **self.object[1])
            return True
        return False
-    
+
    def get_sourcename(self) -> str:
        return self.object.source.split(":")[0]
-    
+
    def format_name(self) -> str:
        return self.object.name

    def format_signature(self, **kwargs: Any) -> str:
        return self.groupname + self.fullname + self.attribute
-    
+
    def add_directive_header(self, sig: str) -> None:
        domain = getattr(self, 'domain', self.objtype)
        directive = getattr(self, 'directivetype', 'def')
@ -310,7 +310,7 @@ class YosysCellDocumenter(YosysCellGroupDocumenter):

        if self.options.noindex:
            self.add_line('   :noindex:', sourcename)
-    
+
    def add_content(self, more_content: Any | None) -> None:
        # set sourcename and add content from attribute documentation
        sourcename = self.get_sourcename()
@ -360,7 +360,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter):
        if isinstance(parent, YosysCellDocumenter):
            return True
        return False
-    
+
    def add_directive_header(self, sig: str) -> None:
        domain = getattr(self, 'domain', 'cell')
        directive = getattr(self, 'directivetype', 'source')
@ -383,7 +383,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter):

        if self.options.noindex:
            self.add_line('   :noindex:', sourcename)
-    
+
    def add_content(self, more_content: Any | None) -> None:
        # set sourcename and add content from attribute documentation
        sourcename = self.get_sourcename()
--- a/docs/util/cmd_documenter.py
+++ b/docs/util/cmd_documenter.py
@ -78,7 +78,7 @@ class YosysCmd:
        self.source_func = source_func
        self.experimental_flag = experimental_flag
        self.internal_flag = internal_flag
-    
+
 class YosysCmdGroupDocumenter(Documenter):
    objtype = 'cmdgroup'
    priority = 10
@ -112,7 +112,7 @@ class YosysCmdGroupDocumenter(Documenter):
            for (name, obj) in cmds_obj.get(self.lib_key, {}).items():
                self.__cmd_lib[name] = obj
        return self.__cmd_lib
-    
+
    @classmethod
    def can_document_member(
        cls,
@ -128,7 +128,7 @@ class YosysCmdGroupDocumenter(Documenter):
            self.content_indent = ''
        self.fullname = self.modname = self.name
        return True
-    
+
    def import_object(self, raiseerror: bool = False) -> bool:
        # get cmd
        try:
@ -140,19 +140,19 @@ class YosysCmdGroupDocumenter(Documenter):

        self.real_modname = self.modname
        return True
-    
+
    def get_sourcename(self) -> str:
        return self.env.doc2path(self.env.docname)
-    
+
    def format_name(self) -> str:
        return self.options.caption or ''

    def format_signature(self, **kwargs: Any) -> str:
        return self.modname
-    
+
    def add_directive_header(self, sig: str) -> None:
        pass
-    
+
    def add_content(self, more_content: Any | None) -> None:
        pass

@ -323,7 +323,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter):
            return self.object.source_file
        except AttributeError:
            return super().get_sourcename()
-    
+
    def format_name(self) -> str:
        return self.object.name

@ -347,7 +347,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter):

        if self.options.noindex:
            self.add_line('   :noindex:', source_name)
-    
+
    def add_content(self, more_content: Any | None) -> None:
        # set sourcename and add content from attribute documentation
        domain = getattr(self, 'domain', self.objtype)
--- a/docs/util/custom_directives.py
+++ b/docs/util/custom_directives.py
@ -21,7 +21,7 @@ from sphinx.util.nodes import make_refnode
 from sphinx.util.docfields import Field, GroupedField
 from sphinx import addnodes

-class TocNode(ObjectDescription):    
+class TocNode(ObjectDescription):
    def add_target_and_index(
        self,
        name: str,
@ -64,7 +64,7 @@ class NodeWithOptions(TocNode):
    doc_field_types = [
        GroupedField('opts', label='Options', names=('option', 'options', 'opt', 'opts')),
    ]
-    
+
    def transform_content(self, contentnode: addnodes.desc_content) -> None:
        """hack `:option -thing: desc` into a proper option list with yoscrypt highlighting"""
        newchildren = []
@ -290,7 +290,7 @@ class CellNode(TocNode):
                         self.env.docname,
                         idx,
                         0))
-            
+
    def transform_content(self, contentnode: addnodes.desc_content) -> None:
        # Add the cell title to the body
        if 'title' in self.options:
@ -380,7 +380,7 @@ class CellSourceNode(TocNode):
                    # only add target and index entry if this is the first
                    # description of the object with this name in this desc block
                    self.add_target_and_index(name, sig, signode)
-        
+
        # handle code
        code = '\n'.join(self.content)
        literal: Element = nodes.literal_block(code, code)
@ -420,11 +420,11 @@ class CellGroupNode(TocNode):

 class TagIndex(Index):
    """A custom directive that creates a tag matrix."""
-    
+
    name = 'tag'
    localname = 'Tag Index'
    shortname = 'Tag'
-    
+
    def __init__(self, *args, **kwargs):
        super(TagIndex, self).__init__(*args, **kwargs)

@ -458,14 +458,14 @@ class TagIndex(Index):
        objs = {name: (dispname, typ, docname, anchor)
                for name, dispname, typ, docname, anchor, prio
                in self.domain.get_objects()}
-        
+
        tmap = {}
        tags = self.domain.data[f'obj2{self.name}']
        for name, tags in tags.items():
            for tag in tags:
                tmap.setdefault(tag,[])
                tmap[tag].append(name)
-            
+
        for tag in tmap.keys():
            lis = content.setdefault(tag, [])
            objlis = tmap[tag]
@ -480,11 +480,11 @@ class TagIndex(Index):

        return (ret, True)

-class CommandIndex(Index):    
+class CommandIndex(Index):
    name = 'cmd'
    localname = 'Command Reference'
    shortname = 'Command'
-    
+
    def __init__(self, *args, **kwargs):
        super(CommandIndex, self).__init__(*args, **kwargs)

@ -525,7 +525,7 @@ class CommandIndex(Index):
            lis.append((
                dispname, 0, docname,
                anchor,
-                '', '', title 
+                '', '', title
            ))
        ret = [(k, v) for k, v in sorted(content.items())]

@ -538,7 +538,7 @@ class CellIndex(CommandIndex):

 class PropIndex(TagIndex):
    """A custom directive that creates a properties matrix."""
-    
+
    name = 'prop'
    localname = 'Property Index'
    shortname = 'Prop'
@ -659,7 +659,7 @@ class CommandDomain(Domain):
        else:
            print(f"Missing ref for {target} in {fromdocname} ")
            return None
-        
+
 class CellDomain(CommandDomain):
    name = 'cell'
    label = 'Yosys internal cells'
@ -730,8 +730,8 @@ def setup(app: Sphinx):
        ('cell-prop', '')

    app.add_role('autoref', autoref)
-    
+
    return {
-        'version': '0.3',    
+        'version': '0.3',
        'parallel_read_safe': False,
    }
--- a/examples/basys3/README
+++ b/examples/basys3/README
@ -16,4 +16,3 @@ Programming board:

 All of the above:
  bash run.sh
-
--- a/examples/basys3/example.xdc
+++ b/examples/basys3/example.xdc
@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK

 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
-
--- a/examples/cmos/README
+++ b/examples/cmos/README
@ -10,4 +10,3 @@ Each test bench can be run separately by either running:

 The later case also includes pure verilog simulation using the iverilog
 and gtkwave for comparison.
-
--- a/examples/cmos/cmos_cells.sp
+++ b/examples/cmos/cmos_cells.sp
@ -36,4 +36,3 @@ X1 nC D t DLATCH
 X2 C t Q DLATCH
 X3 C nC NOT
 .ENDS DFF
-
--- a/examples/cmos/cmos_cells.v
+++ b/examples/cmos/cmos_cells.v
@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R)
 	else
 		Q <= D;
 endmodule
-
--- a/examples/cmos/cmos_cells_digital.sp
+++ b/examples/cmos/cmos_cells_digital.sp
@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1
 .model dff1 d_dff
 Adff D C null null Q nQ dff1
 .ENDS DFF
-
--- a/examples/cmos/counter_digital.ys
+++ b/examples/cmos/counter_digital.ys
@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;;

 write_verilog synth.v
 write_spice -neg 0s -pos 1s synth.sp
-
--- a/examples/cmos/testbench.sh
+++ b/examples/cmos/testbench.sh
@ -4,4 +4,3 @@ set -ex

 ../../yosys counter.ys
 ngspice testbench.sp
-
--- a/examples/cmos/testbench_digital.sh
+++ b/examples/cmos/testbench_digital.sh
@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v

 # requires ngspice with xspice support enabled:
 ngspice testbench_digital.sp
-
--- a/examples/cxx-api/demomain.cc
+++ b/examples/cxx-api/demomain.cc
@ -19,4 +19,3 @@ int main()
 	Yosys::yosys_shutdown();
 	return 0;
 }
-
--- a/examples/gowin/README
+++ b/examples/gowin/README
@ -14,4 +14,3 @@ gowinTool_linux directory

 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to
 the full path to the license file.
-
--- a/examples/gowin/demo.cst
+++ b/examples/gowin/demo.cst
@ -7,4 +7,4 @@ IO_LOC "leds[3]" 82;
 IO_LOC "leds[4]" 83;
 IO_LOC "leds[5]" 84;
 IO_LOC "leds[6]" 85;
-IO_LOC "leds[7]" 86;
+IO_LOC "leds[7]" 86;
--- a/examples/intel/DE2i-150/quartus_compile/de2i.qsf
+++ b/examples/intel/DE2i-150/quartus_compile/de2i.qsf
@ -1096,4 +1096,4 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/examples/intel/MAX10/runme_postsynth
+++ b/examples/intel/MAX10/runme_postsynth
@ -2,4 +2,3 @@

 iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
 vvp -N verif_post
-
--- a/examples/intel/asicworld_lfsr/lfsr_updown.v
+++ b/examples/intel/asicworld_lfsr/lfsr_updown.v
@ -10,7 +10,7 @@ overflow      // Overflow output

 input clk;
 input reset;
- input enable; 
+ input enable;
 input up_down;

 output [7 : 0] count;
@ -18,11 +18,11 @@ overflow      // Overflow output

 reg [7 : 0] count;

- assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : 
+ assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) :
                               (count == {1'b1, {7{1'b0}}}) ;

 always @(posedge clk)
- if (reset) 
+ if (reset)
    count <= {7{1'b0}};
 else if (enable) begin
    if (up_down) begin
--- a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v
+++ b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v
@ -31,4 +31,4 @@ lfsr_updown U(
 .overflow ( overflow )
 );

-endmodule 
+endmodule
--- a/examples/intel/asicworld_lfsr/runme_postsynth
+++ b/examples/intel/asicworld_lfsr/runme_postsynth
@ -2,4 +2,3 @@

 iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
 vvp -N verif_post
-
--- a/examples/intel/asicworld_lfsr/runme_presynth
+++ b/examples/intel/asicworld_lfsr/runme_presynth
@ -2,4 +2,4 @@

 iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\

-vvp -N presynth
+vvp -N presynth
--- a/examples/osu035/Makefile
+++ b/examples/osu035/Makefile
@ -10,4 +10,3 @@ osu035_stdcells.lib:
 clean:
 	rm -f osu035_stdcells.lib
 	rm -f example.yslog example.edif
-
--- a/examples/smtbmc/Makefile
+++ b/examples/smtbmc/Makefile
@ -74,4 +74,3 @@ clean:
 	rm -f glift_mux.ys

 .PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean
-
--- a/examples/smtbmc/demo9.v
+++ b/examples/smtbmc/demo9.v
@ -10,4 +10,3 @@ module demo9;
 		cover(1);
 	end
 endmodule
-
--- a/Show more
+++ b/Show more