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Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745

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Fix  `chparam` values are unsigned when using read_verilog frontend
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nella 2026-06-18 16:50:22 +00:00 • committed by GitHub
commit c99a037c33
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5 changed files with 36 additions and 2 deletions
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1
passes/cmds/setattr.cc
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@ -41,6 +41,7 @@ struct setunset_t
if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value))
log_cmd_error("Can't decode value '%s'!\n", set_value);
value = sig_value.as_const();
value.tag_bare_integer_const(set_value);
}
}
};

8
passes/hierarchy/hierarchy.cc
View file

@ -985,7 +985,9 @@ struct HierarchyPass : public Pass {
SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
log_cmd_error("Can't decode value '%s'!\n", para.second);
top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
RTLIL::Const c = sig_value.as_const();
c.tag_bare_integer_const(para.second);
top_parameters[RTLIL::escape_id(para.first)] = c;
}
}
@ -1073,7 +1075,9 @@ struct HierarchyPass : public Pass {
SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
log_cmd_error("Can't decode value '%s'!\n", para.second);
top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
RTLIL::Const c = sig_value.as_const();
c.tag_bare_integer_const(para.second);
top_parameters[RTLIL::escape_id(para.first)] = c;
}
top_mod = design->module(top_mod->derive(design, top_parameters));