This Fixes the slow downs I observed in techmap.v, which we
attempted to fix via the simplify ast.h route originally. This
turned out to be rather complex though.
By moving $pmux to simplemap we can just avoid that code. My
test case now runs in 310s which is 40s faster than the baseline
change.
B:507898959
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never
matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN
condition on the line above. This caused data bits 68-69 to be
silently overwritten with copies of bits 64-65 on every write.
Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu
(RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2
equivalents correctly use == 36.
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
According to the latest documentation from GOWIN -
"UG285-1.4E Gowin BSRAM & SSRAM User Guide"
The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A
series) does not support the read-before-write mode (WRITE_MODE = 2)
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
