Miodrag Milanović
3b9f06c130
Merge pull request #5447 from pu-cc/gatemate-fix-serdes-cdr
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gatemate: fix SERDES CDR parameters
2025-10-28 09:54:13 +01:00
Patrick Urban
14c1802b01
gatemate: fix SERDES CDR parameters
2025-10-27 15:47:48 +01:00
github-actions[bot]
8bc63ef6da
Bump version
2025-10-26 00:25:16 +00:00
YRabbit
3956f103a9
Gowin. Handle the WRITE_MODE.
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Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-25 23:15:23 +01:00
github-actions[bot]
f5c9e122de
Bump version
2025-10-24 00:21:47 +00:00
YRabbit
64700dec65
Gowin. Disable unsupported BSRAM mode in GW5A
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All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-23 09:59:56 +01:00
Miodrag Milanović
2613c1c0a9
Merge pull request #5438 from cr1901/posix-bugpoint
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Add sys/wait.h header to bugpoint to bring in constants.
2025-10-22 12:40:26 +02:00
github-actions[bot]
37875fdedf
Bump version
2025-10-21 00:23:46 +00:00
William D. Jones
311a2739f6
Add sys/wait.h header to bugpoint to bring in constants.
2025-10-20 19:50:18 -04:00
Jannis Harder
f6fb423ee8
Merge pull request #5430 from YosysHQ/micko/sim_cycle_width
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sim: Make cycle width small as possible and configurable
2025-10-20 18:51:32 +02:00
Jannis Harder
6a0ee6e4fb
Revert sim's cycle_width default back to 10, but keep -width option
2025-10-20 14:40:05 +02:00
github-actions[bot]
1598771a37
Bump version
2025-10-19 00:26:17 +00:00
Mohamed Gaber
b510c36162
hotfix: headers mistakenly added to clean target
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- fix `make clean` deleting a number of headers when ENABLE_PYOSYS is set to 1
2025-10-18 14:08:20 +01:00
github-actions[bot]
272aa9cde2
Bump version
2025-10-17 00:23:40 +00:00
Maxim Kudinov
6535995005
synth_gowin: fix help hint style
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8c347826f6
synth_gowin: make help description more clear
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8f6d63c082
synth_gowin: make setundef an off by default option
2025-10-16 11:09:28 +01:00
Miodrag Milanovic
f11a61b32b
sim: Make cycle width small as possible and configurable
2025-10-16 11:37:44 +02:00
Miodrag Milanovic
db8c1878a0
fix dlopen using fs:path with mingw
2025-10-16 08:30:43 +02:00
github-actions[bot]
061b6ce2ad
Bump version
2025-10-16 00:23:57 +00:00
Miodrag Milanović
759996b968
Merge pull request #5427 from donn/plugin_search_paths
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plugins: add search paths
2025-10-15 20:02:05 +02:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec
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Don't stop parsing sigspec after a {} group.
2025-10-15 17:31:11 +02:00
Mohamed Gaber
dce70abd94
plugins: support Windows path delimiters
2025-10-15 15:53:44 +03:00
Mohamed Gaber
e86797f029
plugins: add search path
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This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules.
This addresses https://github.com/YosysHQ/yosys/issues/2545 , allowing Yosys to be better packaged in non-FHS environments such as Nix.
2025-10-15 14:13:25 +03:00
github-actions[bot]
4970ad5a18
Bump version
2025-10-15 00:23:49 +00:00
Robert O'Callahan
e099a7d34a
Don't stop parsing sigspec after a {} group.
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Resolves #5424
2025-10-14 21:18:58 +00:00
Miodrag Milanović
2e3bfca294
Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns
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verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-14 17:05:31 +02:00
Miodrag Milanović
a89c5b97d8
Merge pull request #5423 from YosysHQ/update_abc
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Update abc
2025-10-14 17:05:13 +02:00
Emil J
a5960ce515
Merge pull request #5197 from YosysHQ/emil/opensta-verilog-export
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OpenSTA verilog compatibility
2025-10-14 16:46:37 +02:00
Miodrag Milanovic
7d2857b30f
Fix regex checks
2025-10-14 16:04:56 +02:00
N. Engelhardt
4513783a02
add tests
2025-10-14 15:48:16 +02:00
Emil J. Tywoniak
e9aedf505c
chtype: replace publish pass with chtype -publish_icells
2025-10-14 15:01:48 +02:00
Miodrag Milanovic
d92cf2f5b0
Compile abc when submodule updates
2025-10-14 14:54:56 +02:00
Miodrag Milanovic
d3d3a9f1ea
Update ABC
2025-10-14 14:47:17 +02:00
Emil J
109abd3224
Merge pull request #5421 from YosysHQ/emil/sort-pass
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sort: init
2025-10-14 10:51:25 +02:00
github-actions[bot]
25f2a88770
Bump version
2025-10-14 00:22:29 +00:00
Emil J. Tywoniak
e5edd2acdb
sort: init
2025-10-13 17:32:26 +02:00
Emil J
71eadc9ab5
Merge pull request #5418 from yrabbit/gw5-dff-and-memory
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Gowin. Reduce the range of flip-flop types.
2025-10-13 17:26:56 +02:00
Emil J. Tywoniak
c46df9ffdc
box_derive: rename -apply to -apply_derived_type
2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
d7cea2c35c
box_derive: add -apply
2025-10-13 17:24:32 +02:00
Emil J. Tywoniak
7d8f92e198
publish: add pass for renaming private cell types to public
2025-10-13 17:24:32 +02:00
Jannis Harder
84b5ec856e
Merge pull request #4320 from YosysHQ/ywb_asserts
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write_btor: Include `$assert` and `$assume` cells in -ywmap output
2025-10-13 15:30:11 +02:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
Miodrag Milanovic
2f8f421dee
verifix: fix bits() deprecation warnings
2025-10-13 09:47:18 +02:00
YRabbit
02e40e8118
Gowin. Reduce the range of flip-flop types.
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UG303-1.0E_Arora Ⅴ Configurable Function Unit (CFU) User Guide.pdf
specifies that the only flip-flop types supported in GW5 are DFFSE,
DFFRE, DFFPE, and DFFCE.
However, the bit streams generated by the vendor IDE also contain DFF
flip-flops, which are probably the result of optimisation, so we leave
them in the list of permitted items, but add a flag that will allow the
generation of completely correct output files, acceptable for further P&
R using vendor tools (they will not allow the use of flip-flops other
than the four specified in the netlist).
In the GW5 SemiDual Port BSRAM series, the primitive does not have
RESETA and RESETB ports—they are replaced by the RESET port, so we
separate the files for BSRAM generation, especially since in the future
we may have to take into account other, as yet unexplored, differences
in BSRAM.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-11 21:12:35 +10:00
Emil J
9a12d92551
Merge pull request #5386 from YosysHQ/emil/liberty-glob-all
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Expand wildcards in Liberty file consumers
2025-10-09 20:21:48 +02:00
Krystine Sherwin
1a0b5d8ea7
write_btor: Include $assert and $assume cells in -ywmap output
2025-10-09 14:50:36 +02:00
github-actions[bot]
89f32a415b
Bump version
2025-10-09 00:22:39 +00:00
