mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Merge pull request #5056 from secworks/blocking_assignment_gatemate_cells_sim

Browse source 
Change to blocking assignments in non-clocked process.
This commit is contained in:
Emil J 2025-04-23 23:13:54 +02:00 • committed by GitHub
commit f8c027b70e
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/gatemate/cells_sim.v
View file

@ -292,10 +292,10 @@ module CC_DLT #(
always @(*)
begin
if (sr) begin
Q <= SR_VAL;
Q = SR_VAL;
end
else if (en) begin
Q <= D;
Q = D;
end
end
@ -407,7 +407,7 @@ module CC_MULT #(
);
always @(*)
begin
P <= A * B;
P = A * B;
end
endmodule