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Changing non clocked alway assignment to blocking.

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2025-04-23 16:59:53 +02:00
parent bf20bc0848
commit e4d6781088
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1 changed files with 1 additions and 1 deletions
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techlibs/ecp5/cells_sim.v
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@ -386,7 +386,7 @@ module TRELLIS_IO(
);
parameter DIR = "INPUT";
reg T_pd;
always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
always @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;
generate
if (DIR == "INPUT") begin