4924 commits

Author	SHA1	Message	Date
Emil J	73e15f2144	Merge pull request #5851 from YosysHQ/emil/share-remove-force ... share: remove -force	2026-05-05 09:06:16 +00:00
Emil J. Tywoniak	7fa660fc60	share: remove -force	2026-05-04 21:34:19 +02:00
bin	5dfe1937a0	Upgrade to WASI SDK 33 and enable exceptions	2026-05-01 13:30:43 -04:00
Ethan Mahintorabi	805c302411	simplemap: Moves $pmux mapping from techmap.v to simple map ... This Fixes the slow downs I observed in techmap.v, which we attempted to fix via the simplify ast.h route originally. This turned out to be rather complex though. By moving $pmux to simplemap we can just avoid that code. My test case now runs in 310s which is 40s faster than the baseline change. B:507898959 Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>	2026-04-29 21:20:39 +00:00
nella	92287d4857	Merge pull request #5841 from YosysHQ/nella/fix-liberty ... Fix ABC: Merged scl conversion failed, using liberty format warning when using -genlib.	2026-04-28 16:43:25 +00:00
nella	d2f7fecef5	Fix liberty cache warning with -genlib.	2026-04-28 15:21:54 +02:00
Emil J	627b691578	Merge pull request #5831 from stashcroft/main ... Make sure co-simulation only uses integer arithmetic	2026-04-27 14:03:58 +00:00
Emil J	30a914167f	Merge pull request #5809 from QuantamHD/pmux_on2 ... opt: Remove O(n²) opt routines across the codebase for pmux	2026-04-24 19:03:40 +00:00
Emil J. Tywoniak	e0b833ac1a	opt_muxtree: dense knowledge	2026-04-24 11:07:58 +02:00
Emil J. Tywoniak	4abaca273e	opt_reduce: further optimization	2026-04-24 11:07:58 +02:00
Scott Ashcroft	23a05fcf35	Add comments to make sure it is clear scale is an exponent of 10	2026-04-23 17:22:14 +01:00
Scott Ashcroft	e69341cd5f	Make sure co-simulation only uses integer arithmetic	2026-04-23 17:22:14 +01:00
nella	d795a4f1d2	Fix WASI, store in temp dir.	2026-04-23 12:43:43 +02:00
nella	afac9a28b0	Fix WASI build.	2026-04-23 12:43:43 +02:00
nella	5d4d94a5dd	Fix mac compile.	2026-04-23 12:43:43 +02:00
nella	94a215b4f7	Add dont_use_cells to scl cache.	2026-04-23 12:43:43 +02:00
nella	edd3ad525e	Add scl caching to abc_new.	2026-04-23 12:43:43 +02:00
nella	9143178343	Merge liberty files into stripped scl files.	2026-04-23 12:43:43 +02:00
N. Engelhardt	240f7030b2	xprop: ignore $scopeinfo cells	2026-04-21 10:52:50 +02:00
Emil J. Tywoniak	b4c081c70b	abc: fix deferred logs	2026-04-17 13:35:47 +02:00
nella	4506dffa9f	Fix use after free.	2026-04-13 12:48:05 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
nella	c3c577f333	Fix test cases.	2026-04-13 12:48:05 +02:00
nella	135812ab02	Further CSA cleanup.	2026-04-13 12:48:05 +02:00
nella	847a8941e9	Clang-Format CSA tree.	2026-04-13 12:48:05 +02:00
nella	a02c238874	Consolidate Wallace from booth and CSA.	2026-04-13 12:48:05 +02:00
nella	4bbffecf98	Invert.	2026-04-13 12:48:05 +02:00
nella	42c309347b	Clarify.	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6d656e932	csa_tree: move to techmap	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6a8feec22	csa_tree: refactor	2026-04-13 12:48:05 +02:00
nella	67e145618b	Replace utf arrow with ascii arrow.	2026-04-13 12:48:05 +02:00
nella	5d90bcc792	CSA add support for macc and alu cells.	2026-04-13 12:48:05 +02:00
nella	335cce4895	Add sub chain support for csa trees.	2026-04-13 12:48:05 +02:00
nella	e69914b8be	better balancing.	2026-04-13 12:48:05 +02:00
nella	46df888191	impl csa tree.	2026-04-13 12:48:05 +02:00
Lofty	564c617721	Merge pull request #5790 from Eiko-Eira/main ... Fixed typos and incorrect grammar	2026-04-11 03:26:55 +00:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
Emil J. Tywoniak	41b69df2cb	abc_new: stable TopoSort	2026-04-06 15:09:52 +02:00
Noah Van Dijk	52243e10fb	Fix typo in pmgen/README.md ... Line 161: calulated > calculated	2026-04-02 10:24:31 -05:00
Emil J	cede13a742	Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port ... muxpack: fix wide Y port handling	2026-03-31 10:49:39 +00:00
tondapusili	5b22e64d19	sim: cache sigmap in register_output_step_values	2026-03-24 16:10:11 -07:00
Miodrag Milanović	66306a8ca3	Merge pull request #5769 from Silimate/optimize_sim_pass ... sim: early return from checkSignals in sim mode	2026-03-23 17:19:26 +00:00
Emil J	b44188110b	Merge pull request #5764 from YosysHQ/emil/constmap-error ... constmap: error if no -cell set	2026-03-23 15:15:04 +00:00
tondapusili	69219e6be0	sim: early-return from checkSignals in sim mode	2026-03-20 12:32:49 -07:00
Lofty	f560cba952	Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 ... abc9: remove -fast [sc-269]	2026-03-19 08:41:45 +00:00
Lofty	27210627e5	abc9: remove -fast	2026-03-19 07:30:23 +00:00
Lofty	8d1d5a25e5	Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2 ... abc: remove -S [sc-269]	2026-03-19 07:26:54 +00:00
Lofty	05de1c4ae2	Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4 ... abc9: remove abc9.if.C [sc-269]	2026-03-19 07:26:37 +00:00
Emil J. Tywoniak	4f4672d17b	muxpack: fix wide Y port handling	2026-03-19 00:12:49 +01:00
Emil J. Tywoniak	7aaa0621d3	constmap: error if no -cell set	2026-03-19 00:01:14 +01:00