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Proc: Use selections consistently

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All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively.
This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
This commit is contained in:
Krystine Sherwin 2025-05-31 12:04:42 +12:00
parent 545753cc5a
commit ab0e3cc05f
No known key found for this signature in database
10 changed files with 69 additions and 98 deletions
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63
passes/proc/proc_arst.cc
View file

@ -288,43 +288,40 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
pool<Wire*> delete_initattr_wires;
for (auto mod : design->modules())
if (design->selected(mod)) {
SigMap assign_map(mod);
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
proc_arst(mod, proc_it.second, assign_map);
if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs)
if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
delete_initattr_wires.insert(chunk.wire);
}
if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n",
proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
for (auto mod : design->all_selected_modules()) {
SigMap assign_map(mod);
for (auto proc : mod->selected_processes()) {
proc_arst(mod, proc, assign_map);
if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc->syncs)
if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
delete_initattr_wires.insert(chunk.wire);
}
if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n",
proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
}
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod->wire(global_arst);
sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync);
}
}
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod->wire(global_arst);
sync->actions = arst_actions;
proc->syncs.push_back(sync);
}
}
}
for (auto wire : delete_initattr_wires)
wire->attributes.erase(ID::init);

18
passes/proc/proc_clean.cc
View file

@ -208,19 +208,15 @@ struct ProcCleanPass : public Pass {
}
extra_args(args, argidx, design);
for (auto mod : design->modules()) {
for (auto mod : design->all_selected_modules()) {
std::vector<RTLIL::Process *> delme;
if (!design->selected(mod))
continue;
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
proc_clean(mod, proc_it.second, total_count, quiet);
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
proc_it.second->root_case.actions.size() == 0) {
for (auto proc : mod->selected_processes()) {
proc_clean(mod, proc, total_count, quiet);
if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
proc->root_case.actions.size() == 0) {
if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
delme.push_back(proc_it.second);
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
delme.push_back(proc);
}
}
for (auto proc : delme) {

12
passes/proc/proc_dff.cc
View file

@ -306,13 +306,11 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design);
for (auto mod : design->modules())
if (design->selected(mod)) {
ConstEval ce(mod);
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_dff(mod, proc_it.second, ce);
}
for (auto mod : design->all_selected_modules()) {
ConstEval ce(mod);
for (auto proc : mod->selected_processes())
proc_dff(mod, proc, ce);
}
}
} ProcDffPass;

9
passes/proc/proc_dlatch.cc
View file

@ -463,11 +463,10 @@ struct ProcDlatchPass : public Pass {
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
proc_dlatch_db_t db(module);
for (auto &proc_it : module->processes)
if (design->selected(module, proc_it.second))
proc_dlatch(db, proc_it.second);
for (auto mod : design->all_selected_modules()) {
proc_dlatch_db_t db(mod);
for (auto proc : mod->selected_processes())
proc_dlatch(db, proc);
db.fixup_muxes();
}
}

12
passes/proc/proc_init.cc
View file

@ -91,13 +91,11 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design);
for (auto mod : design->modules())
if (design->selected(mod)) {
SigMap sigmap(mod);
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_init(mod, sigmap, proc_it.second);
}
for (auto mod : design->all_selected_modules()) {
SigMap sigmap(mod);
for (auto proc : mod->selected_processes())
proc_init(mod, sigmap, proc);
}
}
} ProcInitPass;

9
passes/proc/proc_memwr.cc
View file

@ -99,9 +99,9 @@ struct ProcMemWrPass : public Pass {
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
for (auto mod : design->all_selected_modules()) {
dict<IdString, int> next_port_id;
for (auto cell : module->cells()) {
for (auto cell : mod->cells()) {
if (cell->type.in(ID($memwr), ID($memwr_v2))) {
bool is_compat = cell->type == ID($memwr);
IdString memid = cell->parameters.at(ID::MEMID).decode_string();
@ -110,9 +110,8 @@ struct ProcMemWrPass : public Pass {
next_port_id[memid] = port_id + 1;
}
}
for (auto &proc_it : module->processes)
if (design->selected(module, proc_it.second))
proc_memwr(module, proc_it.second, next_port_id);
for (auto proc : mod->selected_processes())
proc_memwr(mod, proc, next_port_id);
}
}
} ProcMemWrPass;

8
passes/proc/proc_mux.cc
View file

@ -468,11 +468,9 @@ struct ProcMuxPass : public Pass {
}
extra_args(args, argidx, design);
for (auto mod : design->modules())
if (design->selected(mod))
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_mux(mod, proc_it.second, ifxmode);
for (auto mod : design->all_selected_modules())
for (auto proc : mod->selected_processes())
proc_mux(mod, proc, ifxmode);
}
} ProcMuxPass;

11
passes/proc/proc_prune.cc
View file

@ -127,15 +127,10 @@ struct ProcPrunePass : public Pass {
extra_args(args, 1, design);
for (auto mod : design->modules()) {
if (!design->selected(mod))
continue;
for (auto mod : design->all_selected_modules()) {
PruneWorker worker(mod);
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
worker.do_process(proc_it.second);
}
for (auto proc : mod->selected_processes())
worker.do_process(proc);
total_removed_count += worker.removed_count;
total_promoted_count += worker.promoted_count;
}

14
passes/proc/proc_rmdead.cc
View file

@ -147,21 +147,17 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design);
int total_counter = 0;
for (auto mod : design->modules()) {
if (!design->selected(mod))
continue;
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
for (auto mod : design->all_selected_modules()) {
for (auto proc : mod->selected_processes()) {
int counter = 0, full_case_counter = 0;
for (auto switch_it : proc_it.second->root_case.switches)
for (auto switch_it : proc->root_case.switches)
proc_rmdead(switch_it, counter, full_case_counter);
if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter,
log_id(proc_it.first), log_id(mod));
log_id(proc), log_id(mod));
if (full_case_counter > 0)
log("Marked %d switch rules as full_case in process %s in module %s.\n",
full_case_counter, log_id(proc_it.first), log_id(mod));
full_case_counter, log_id(proc), log_id(mod));
total_counter += counter;
}
}

11
passes/proc/proc_rom.cc
View file

@ -243,15 +243,10 @@ struct ProcRomPass : public Pass {
extra_args(args, 1, design);
for (auto mod : design->modules()) {
if (!design->selected(mod))
continue;
for (auto mod : design->all_selected_modules()) {
RomWorker worker(mod);
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
worker.do_process(proc_it.second);
}
for (auto proc : mod->selected_processes())
worker.do_process(proc);
total_count += worker.count;
}