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https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
Proc: Use selections consistently
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively. This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
This commit is contained in:
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545753cc5a
commit
ab0e3cc05f
10 changed files with 69 additions and 98 deletions
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@ -288,43 +288,40 @@ struct ProcArstPass : public Pass {
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extra_args(args, argidx, design);
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pool<Wire*> delete_initattr_wires;
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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SigMap assign_map(mod);
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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proc_arst(mod, proc_it.second, assign_map);
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if (global_arst.empty() || mod->wire(global_arst) == nullptr)
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continue;
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std::vector<RTLIL::SigSig> arst_actions;
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for (auto sync : proc_it.second->syncs)
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
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for (auto &act : sync->actions) {
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RTLIL::SigSpec arst_sig, arst_val;
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for (auto &chunk : act.first.chunks())
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if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
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RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
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value.extend_u0(chunk.wire->width, false);
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arst_sig.append(chunk);
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arst_val.append(value.extract(chunk.offset, chunk.width));
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delete_initattr_wires.insert(chunk.wire);
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}
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if (arst_sig.size()) {
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log("Added global reset to process %s: %s <- %s\n",
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proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val));
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arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
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for (auto mod : design->all_selected_modules()) {
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SigMap assign_map(mod);
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for (auto proc : mod->selected_processes()) {
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proc_arst(mod, proc, assign_map);
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if (global_arst.empty() || mod->wire(global_arst) == nullptr)
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continue;
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std::vector<RTLIL::SigSig> arst_actions;
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for (auto sync : proc->syncs)
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
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for (auto &act : sync->actions) {
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RTLIL::SigSpec arst_sig, arst_val;
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for (auto &chunk : act.first.chunks())
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if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
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RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
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value.extend_u0(chunk.wire->width, false);
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arst_sig.append(chunk);
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arst_val.append(value.extract(chunk.offset, chunk.width));
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delete_initattr_wires.insert(chunk.wire);
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}
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if (arst_sig.size()) {
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log("Added global reset to process %s: %s <- %s\n",
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proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val));
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arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
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}
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if (!arst_actions.empty()) {
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RTLIL::SyncRule *sync = new RTLIL::SyncRule;
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sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
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sync->signal = mod->wire(global_arst);
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sync->actions = arst_actions;
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proc_it.second->syncs.push_back(sync);
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}
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}
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if (!arst_actions.empty()) {
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RTLIL::SyncRule *sync = new RTLIL::SyncRule;
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sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
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sync->signal = mod->wire(global_arst);
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sync->actions = arst_actions;
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proc->syncs.push_back(sync);
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}
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}
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}
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for (auto wire : delete_initattr_wires)
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wire->attributes.erase(ID::init);
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@ -208,19 +208,15 @@ struct ProcCleanPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto mod : design->modules()) {
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for (auto mod : design->all_selected_modules()) {
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std::vector<RTLIL::Process *> delme;
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if (!design->selected(mod))
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continue;
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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proc_clean(mod, proc_it.second, total_count, quiet);
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if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
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proc_it.second->root_case.actions.size() == 0) {
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for (auto proc : mod->selected_processes()) {
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proc_clean(mod, proc, total_count, quiet);
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if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
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proc->root_case.actions.size() == 0) {
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if (!quiet)
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log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
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delme.push_back(proc_it.second);
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log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
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delme.push_back(proc);
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}
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}
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for (auto proc : delme) {
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@ -306,13 +306,11 @@ struct ProcDffPass : public Pass {
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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ConstEval ce(mod);
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_dff(mod, proc_it.second, ce);
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}
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for (auto mod : design->all_selected_modules()) {
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ConstEval ce(mod);
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for (auto proc : mod->selected_processes())
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proc_dff(mod, proc, ce);
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}
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}
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} ProcDffPass;
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@ -463,11 +463,10 @@ struct ProcDlatchPass : public Pass {
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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proc_dlatch_db_t db(module);
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for (auto &proc_it : module->processes)
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if (design->selected(module, proc_it.second))
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proc_dlatch(db, proc_it.second);
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for (auto mod : design->all_selected_modules()) {
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proc_dlatch_db_t db(mod);
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for (auto proc : mod->selected_processes())
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proc_dlatch(db, proc);
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db.fixup_muxes();
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}
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}
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@ -91,13 +91,11 @@ struct ProcInitPass : public Pass {
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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SigMap sigmap(mod);
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_init(mod, sigmap, proc_it.second);
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}
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for (auto mod : design->all_selected_modules()) {
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SigMap sigmap(mod);
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for (auto proc : mod->selected_processes())
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proc_init(mod, sigmap, proc);
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}
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}
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} ProcInitPass;
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@ -99,9 +99,9 @@ struct ProcMemWrPass : public Pass {
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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for (auto mod : design->all_selected_modules()) {
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dict<IdString, int> next_port_id;
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for (auto cell : module->cells()) {
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for (auto cell : mod->cells()) {
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if (cell->type.in(ID($memwr), ID($memwr_v2))) {
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bool is_compat = cell->type == ID($memwr);
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IdString memid = cell->parameters.at(ID::MEMID).decode_string();
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@ -110,9 +110,8 @@ struct ProcMemWrPass : public Pass {
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next_port_id[memid] = port_id + 1;
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}
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}
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for (auto &proc_it : module->processes)
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if (design->selected(module, proc_it.second))
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proc_memwr(module, proc_it.second, next_port_id);
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for (auto proc : mod->selected_processes())
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proc_memwr(mod, proc, next_port_id);
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}
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}
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} ProcMemWrPass;
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@ -468,11 +468,9 @@ struct ProcMuxPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto mod : design->modules())
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if (design->selected(mod))
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_mux(mod, proc_it.second, ifxmode);
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for (auto mod : design->all_selected_modules())
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for (auto proc : mod->selected_processes())
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proc_mux(mod, proc, ifxmode);
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}
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} ProcMuxPass;
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@ -127,15 +127,10 @@ struct ProcPrunePass : public Pass {
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extra_args(args, 1, design);
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for (auto mod : design->modules()) {
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if (!design->selected(mod))
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continue;
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for (auto mod : design->all_selected_modules()) {
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PruneWorker worker(mod);
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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worker.do_process(proc_it.second);
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}
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for (auto proc : mod->selected_processes())
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worker.do_process(proc);
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total_removed_count += worker.removed_count;
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total_promoted_count += worker.promoted_count;
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}
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@ -147,21 +147,17 @@ struct ProcRmdeadPass : public Pass {
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extra_args(args, 1, design);
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int total_counter = 0;
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for (auto mod : design->modules()) {
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if (!design->selected(mod))
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continue;
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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for (auto mod : design->all_selected_modules()) {
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for (auto proc : mod->selected_processes()) {
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int counter = 0, full_case_counter = 0;
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for (auto switch_it : proc_it.second->root_case.switches)
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for (auto switch_it : proc->root_case.switches)
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proc_rmdead(switch_it, counter, full_case_counter);
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if (counter > 0)
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log("Removed %d dead cases from process %s in module %s.\n", counter,
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log_id(proc_it.first), log_id(mod));
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log_id(proc), log_id(mod));
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if (full_case_counter > 0)
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log("Marked %d switch rules as full_case in process %s in module %s.\n",
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full_case_counter, log_id(proc_it.first), log_id(mod));
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full_case_counter, log_id(proc), log_id(mod));
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total_counter += counter;
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}
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}
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@ -243,15 +243,10 @@ struct ProcRomPass : public Pass {
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extra_args(args, 1, design);
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for (auto mod : design->modules()) {
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if (!design->selected(mod))
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continue;
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for (auto mod : design->all_selected_modules()) {
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RomWorker worker(mod);
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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worker.do_process(proc_it.second);
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}
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for (auto proc : mod->selected_processes())
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worker.do_process(proc);
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total_count += worker.count;
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}
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