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yosys/passes
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
2025-05-12 12:48:01 +12:00
..
cmds driver: allow --no-version still write things like Generated by Yosys 2025-05-07 11:34:23 +02:00
equiv mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
fsm io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
hierarchy hierarchy: Ignore width mismatch from verific 2025-04-11 04:12:34 +12:00
memory memory_libmap: fix MapWorker memory allocation 2025-04-14 12:41:14 +02:00
opt opt_expr: only sign extend shift arguments for arithmetic right shift 2025-04-26 12:40:04 +02:00
pmgen io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
proc mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
sat sim.cc: Move cycle check 2025-05-12 12:48:01 +12:00
techmap gzip: refactor file open failure errors 2025-04-29 10:37:35 +02:00
tests macc: Rename 'ports' to 'terms' throughout codebase 2025-03-18 13:25:10 +01:00