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Merge pull request #5066 from YosysHQ/george/opt_expr_shr_sign

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opt_expr: fix sign extension for shifts
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KrystalDelusion 2025-04-29 09:29:10 +12:00 • committed by GitHub
commit bfe05965f9
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3 changed files with 58 additions and 7 deletions
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9
passes/opt/opt_expr.cc
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@ -1315,13 +1315,14 @@ skip_fine_alu:
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
// and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX
shift_bits = min(shift_bits, GetSize(sig_a));
if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
// and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX.
// We do this after sign-extending a so this accounts for the output size
shift_bits = min(shift_bits, GetSize(sig_a));
for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits;
if (0 <= idx && idx < GetSize(sig_a))