mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-28 08:58:45 +00:00
Code Activity

Make attrmap able to alter memory attributes as well

Browse source
This commit is contained in:
Miodrag Milanovic 2025-06-04 08:01:21 +02:00
parent 3ef4c91c31
commit 784de0f6e3
1 changed files with 5 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

17
passes/techmap/attrmap.cc
View file

@ -270,26 +270,19 @@ struct AttrmapPass : public Pass {
{
for (auto module : design->selected_modules())
{
for (auto wire : module->selected_wires())
for (auto wire : module->selected_members())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes);
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
for (auto proc : module->processes)
for (auto proc : module->selected_processes())
{
if (!design->selected(module, proc.second))
continue;
attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
std::vector<RTLIL::CaseRule*> all_cases = {&proc->root_case};
while (!all_cases.empty()) {
RTLIL::CaseRule *cs = all_cases.back();
all_cases.pop_back();
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc)), actions, cs->attributes);
for (auto &sw : cs->switches) {
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc)), actions, sw->attributes);
all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
}
}