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2016 commits

Author SHA1 Message Date
Benjamin Barzen
8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2023-04-22 16:24:36 -07:00
Jannis Harder
985f4926b7 verilog: Fix const eval of unbased unsized constants 
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
 2023-04-20 12:12:50 +02:00
Miodrag Milanovic
0f5e7c244d add additional dff and lutram tests 2023-04-06 09:10:14 +02:00
Miodrag Milanovic
54d313efc3 add test for CCU2D 2023-04-06 09:10:14 +02:00
Jannis Harder
fb1c2be76b verilog: Support void functions 
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
 2023-03-20 12:52:46 +01:00
Miodrag Milanovic
61da330a38 Update tests 2023-03-20 09:58:41 +01:00
Jannis Harder
390d1c583a verific: Fix enum_values support and signed attribute values 
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
 2023-03-15 09:51:36 +01:00
Jannis Harder
c50f641812
Merge pull request #3682 from daglem/struct-member-out-of-bounds 
Out of bounds checking for struct/union members
 2023-03-10 16:14:56 +01:00
Dag Lem
1af7d6121f Added test for dynamic indexing within struct members 2023-03-08 20:25:39 +01:00
Dag Lem
0d3423ddea Index struct/union members within corresponding wire chunks 
This guards against access to bits outside of struct/union
members via dynamic indexing.
 2023-03-05 14:54:17 +01:00
Miodrag Milanović
21e87f7986
Merge pull request #3646 from YosysHQ/lofty/fix-3591 
muxcover: do not add decode muxes with x inputs
 2023-02-27 16:26:57 +01:00
N. Engelhardt
842cdad575
Merge pull request #3674 from YosysHQ/fix_wide_case 2023-02-27 16:04:11 +01:00
gatecat
2ab3747cc9 fabulous: Add support for mapping carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-27 09:50:34 +01:00
Miodrag Milanovic
d8cefec169 Added ranged case check 2023-02-27 09:24:04 +01:00
Miodrag Milanovic
53a4f0fb56 Add test example 2023-02-27 09:24:04 +01:00
KrystalDelusion
f80920bd9f Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
KrystalDelusion
445a801a85 bug3205.ys removed 
Made redundant by TDP test(s) in memories.ys
 2023-02-21 05:23:16 +13:00
KrystalDelusion
51c2d476c2 Removing extra default_nettype lines 2023-02-21 05:23:16 +13:00
KrystalDelusion
8f6a06951c Fix for sync_ram_sdp not being final module 
Explicitly declare -top in synth_intel_alm.
 2023-02-21 05:23:16 +13:00
KrystalDelusion
7f033d3c1f More tests in memlib/generate.py 
Covers most of the todo list, at least functionally.  Some minor issues with not always using hardware features.
 2023-02-21 05:23:15 +13:00
KrystalDelusion
af1b9c9e07 Tests for ram_style = "huge" 
iCE40 SPRAM and Xilinx URAM
 2023-02-21 05:23:15 +13:00
KrystalDelusion
de2f140c09 Testing TDP synth mapping 
New common sync_ram_tdp.
Used in ecp5 and gatemate mem*.ys.
 2023-02-21 05:23:15 +13:00
KrystalDelusion
48f4e09202 Asymmetric port ram tests with Xilinx 
Uses verilog code from User Guide 901 (2021.1)
 2023-02-21 05:23:14 +13:00
KrystalDelusion
ac5fa9a838 Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
Dag Lem
79043cb849 Out of bounds checking for struct/union members 
Currently, only constant indices are checked.
 2023-02-19 23:25:08 +01:00
Jannis Harder
1cedad7a68
Merge pull request #3675 from daglem/struct-item-queries 
Support for data and array queries on struct/union item expressions
 2023-02-15 13:33:34 +01:00
Jannis Harder
68480dfa19
Merge pull request #3671 from zachjs/master 
Add test for typenames using constants shadowed later on
 2023-02-15 13:04:43 +01:00
Dag Lem
f8219289b2 Corrected tests for data and array queries on struct/union item expressions 2023-02-15 12:36:29 +01:00
Dag Lem
c1e12877f0 Support for data and array queries on struct/union item expressions 
For now, $bits, $left, $right, $low, $high, and $size are supported.
 2023-02-15 11:44:24 +01:00
Jannis Harder
53bda9de54
Merge pull request #3661 from daglem/struct-array-range-offset 
Handle range offsets in packed arrays within packed structs
 2023-02-15 11:21:56 +01:00
Jannis Harder
ec94703619
Merge pull request #2995 from georgerennie/cover_precond 
chformal: Add -coverenable option
 2023-02-14 17:46:31 +01:00
Jannis Harder
85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions 
equiv_make: Add -make_assert option
 2023-02-14 17:15:55 +01:00
Jannis Harder
d2032ac6fd
Merge pull request #3669 from jix/fix-xprop-tests-yosys-call 
tests: Fix path of yosys invocation in xprop tests
 2023-02-13 17:55:36 +01:00
Jannis Harder
55ad3fe6c7 xprop tests: Make iverilog invocation more portable 2023-02-13 16:54:11 +01:00
Jannis Harder
2a68eee5f1 xprop: Test fixes and abort on test failure 
Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.

This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
 2023-02-13 14:05:16 +01:00
Jannis Harder
9f20beb7df xprop: Smaller subset of tests to run by default 2023-02-13 14:02:02 +01:00
Dag Lem
615adc4253
Resolve package types in interfaces (#3658) 
* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
 2023-02-12 18:25:39 -05:00
Zachary Snow
26a6c60478 Add test for typenames using constants shadowed later on 
This possible edge case came up while reviewing #3555. It is currently
handled correctly, but there is no clear test coverage.
 2023-02-12 17:03:37 -05:00
Jannis Harder
6d021f04d4 tests: Fix path of yosys invocation in xprop tests 
For now xprop test failures are still expected and ignored, but without
this change, they did not even run unless the yosys build was in path.
 2023-02-10 19:17:16 +01:00
Jannis Harder
d31d5da69f tests: in xprop tests, use MAKE variable if set 2023-02-10 15:01:04 +01:00
Dag Lem
777c589e85 Handle range offsets in packed arrays within packed structs 
This brings the metadata for packed arrays in packed structs
in line with the metadata for unpacked arrays, and correctly
handles the case when both lsb and msb in an address range are
non-zero.
 2023-02-05 17:09:51 +01:00
Jannis Harder
c235802f4a
Merge pull request #3650 from jix/rtlil_roundtrip_z_bits 
backends/rtlil: Do not shorten a value with z bits to 'x
 2023-01-30 16:14:24 +01:00
N. Engelhardt
ecfa7e9fbc add pmux option to bmuxmap for better fsm detection with verific frontend 2023-01-30 16:12:53 +01:00
Dag Lem
26db5a11d3 Resolve struct member package types 2023-01-29 13:51:44 -05:00
Dag Lem
db13c6df2b
Handle struct members of union type (#3641) 2023-01-29 13:45:45 -05:00
Jannis Harder
b08a880704 backends/rtlil: Do not shorten a value with z bits to 'x 2023-01-29 14:02:25 +01:00
Lofty
822c7b0341 muxcover: do not add decode muxes with x inputs 2023-01-26 05:19:45 +00:00
Jannis Harder
5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
Jannis Harder
3ebc50dee4
Merge pull request #3467 from jix/fix_cellarray_simplify 
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
 2022-12-19 16:05:13 +01:00
Jannis Harder
cf3570abde simplify: regression test for AST_CELLARRAY simplification issue 2022-12-07 18:41:55 +01:00