Merge pull request #3674 from YosysHQ/fix_wide_case

tests/verific/.gitignore

@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk

tests/verific/case.sv

@@ -0,0 +1,28 @@
+module top (
+	input clk,
+	input [5:0] currentstate,
+	output reg [1:0] o
+	);
+	always @ (posedge clk)
+	begin
+		case (currentstate)
+			5'd1,5'd2, 5'd3: 
+				begin 
+					o <= 2'b01;
+				end	
+			5'd4:
+			  	begin
+					o <= 2'b10;
+				end
+			5'd5,5'd6,5'd7: 
+				begin
+					o <= 2'b11;
+				end
+			default :
+				begin
+					o <= 2'b00;
+				end
+		endcase
+	end
+endmodule
+

tests/verific/case.ys

@@ -0,0 +1,16 @@
+verific -cfg db_abstract_case_statement_synthesis 0
+read -sv case.sv
+verific -import top 
+prep
+rename top gold
+
+verific -cfg db_abstract_case_statement_synthesis 1
+read -sv case.sv
+verific -import top 
+prep
+rename top gate
+
+miter -equiv -flatten -make_assert gold gate miter
+prep -top miter
+clk2fflogic
+sat -set-init-zero -tempinduct -prove-asserts -verify

tests/verific/range_case.sv

@@ -0,0 +1,11 @@
+module top(input clk, input signed [3:0] sel_w , output reg out);
+
+always @ (posedge clk)
+begin
+    case (sel_w) inside
+        [-4:3] : out <= 1'b1;
+        [4:5] : out <= 1'b0;
+    endcase
+end
+
+endmodule

tests/verific/range_case.ys

@@ -0,0 +1,16 @@
+verific -cfg db_abstract_case_statement_synthesis 0
+read -sv range_case.sv
+verific -import top 
+proc
+rename top gold
+
+verific -cfg db_abstract_case_statement_synthesis 1
+read -sv range_case.sv
+verific -import top 
+proc
+rename top gate
+
+miter -equiv -flatten -make_assert gold gate miter
+prep -top miter
+clk2fflogic
+sat -set-init-zero -tempinduct -prove-asserts -verify

tests/verific/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash