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fabulous: Add support for mapping carry chains

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-02-20 12:49:48 +01:00 committed by myrtle
parent 8216b23fb7
commit 2ab3747cc9
5 changed files with 102 additions and 2 deletions

View file

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read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 10 t:LUT4_HA
select -assert-max 4 t:LUT1
select -assert-none t:LUT1 t:LUT4_HA %% t:* %D