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Merge pull request #3646 from YosysHQ/lofty/fix-3591

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muxcover: do not add decode muxes with x inputs
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Miodrag Milanović 2023-02-27 16:26:57 +01:00 • committed by GitHub
commit 21e87f7986
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2 changed files with 41 additions and 4 deletions
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40
tests/various/muxcover.ys
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@ -508,3 +508,43 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
sat -verify -prove-asserts -show-ports miter
## implement a mux6 as a mux8 :: https://github.com/YosysHQ/yosys/issues/3591
design -reset
read_verilog << EOF
module test (A, S, Y);
parameter INPUTS = 6;
input [INPUTS-1:0] A;
input [$clog2(INPUTS)-1:0] S;
wire [15:0] AA = {{(16-INPUTS){1'b0}}, A};
wire [3:0] SS = {{(4-$clog2(INPUTS)){1'b0}}, S};
output Y = SS[3] ? (SS[2] ? SS[1] ? (SS[0] ? AA[15] : AA[14])
: (SS[0] ? AA[13] : AA[12])
: SS[1] ? (SS[0] ? AA[11] : AA[10])
: (SS[0] ? AA[9] : AA[8]))
: (SS[2] ? SS[1] ? (SS[0] ? AA[7] : AA[6])
: (SS[0] ? AA[5] : AA[4])
: SS[1] ? (SS[0] ? AA[3] : AA[2])
: (SS[0] ? AA[1] : AA[0]));
endmodule
EOF
prep
design -save gold
simplemap t:\$mux
muxcover
opt_clean -purge
select -assert-count 1 t:$_MUX8_
select -assert-none t:$_MUX8_ %% t:* %D
techmap -map +/simcells.v t:$_MUX8_
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
sat -verify -prove-asserts -show-ports miter