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add test for CCU2D

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Miodrag Milanovic 2023-04-04 10:56:28 +02:00 committed by myrtle
parent 9e9fae1966
commit 54d313efc3
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tests/arch/machxo2/counter.ys Normal file
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read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:CCU2D
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:CCU2D t:TRELLIS_FF %% t:* %D