mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

muxcover: do not add decode muxes with x inputs

Browse source
This commit is contained in:
Lofty 2023-01-25 09:26:58 +00:00
parent 2e3c08adc4
commit 822c7b0341
2 changed files with 41 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

40
tests/various/muxcover.ys
View file

@ -508,3 +508,43 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
sat -verify -prove-asserts -show-ports miter
## implement a mux6 as a mux8 :: https://github.com/YosysHQ/yosys/issues/3591
design -reset
read_verilog << EOF
module test (A, S, Y);
parameter INPUTS = 6;
input [INPUTS-1:0] A;
input [$clog2(INPUTS)-1:0] S;
wire [15:0] AA = {{(16-INPUTS){1'b0}}, A};
wire [3:0] SS = {{(4-$clog2(INPUTS)){1'b0}}, S};
output Y = SS[3] ? (SS[2] ? SS[1] ? (SS[0] ? AA[15] : AA[14])
: (SS[0] ? AA[13] : AA[12])
: SS[1] ? (SS[0] ? AA[11] : AA[10])
: (SS[0] ? AA[9] : AA[8]))
: (SS[2] ? SS[1] ? (SS[0] ? AA[7] : AA[6])
: (SS[0] ? AA[5] : AA[4])
: SS[1] ? (SS[0] ? AA[3] : AA[2])
: (SS[0] ? AA[1] : AA[0]));
endmodule
EOF
prep
design -save gold
simplemap t:\$mux
muxcover
opt_clean -purge
select -assert-count 1 t:$_MUX8_
select -assert-none t:$_MUX8_ %% t:* %D
techmap -map +/simcells.v t:$_MUX8_
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold gate miter
sat -verify -prove-asserts -show-ports miter