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Merge pull request #3682 from daglem/struct-member-out-of-bounds
Out of bounds checking for struct/union members
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commit
c50f641812
8 changed files with 145 additions and 22 deletions
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@ -75,7 +75,7 @@ generate_tests() {
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if [[ $do_sv = true ]]; then
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for x in *.sv; do
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if [ ! -f "${x%.sv}.ys" ]; then
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generate_ys_test "$x" "-p \"prep -top top; sat -verify -prove-asserts\" $yosys_args"
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generate_ys_test "$x" "-p \"prep -top top; sat -enable_undef -verify -prove-asserts\" $yosys_args"
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fi;
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done
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fi;
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@ -12,12 +12,16 @@ module top;
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s.a[2:1] = 16'h1234;
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s.a[5] = 8'h42;
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s.a[-1] = '0;
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s.b = '1;
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s.b[1:0] = '0;
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end
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always_comb assert(s==64'h4200_0012_3400_FFFC);
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always_comb assert(s.a[0][3:-4]===8'h0x);
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always_comb assert(s.b[23:16]===8'hxx);
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always_comb assert(s.b[19:12]===8'hxf);
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struct packed {
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bit [7:0] [7:0] a; // 8 element packed array of bytes
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67
tests/svtypes/struct_dynamic_range.sv
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67
tests/svtypes/struct_dynamic_range.sv
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@ -0,0 +1,67 @@
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module range_shift_mask(
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input logic [2:0] addr_i,
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input logic [7:0] data_i,
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input logic [2:0] addr_o,
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output logic [7:0] data_o
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);
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// (* nowrshmsk = 0 *)
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struct packed {
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logic [7:0] msb;
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logic [0:3][7:0] data;
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logic [7:0] lsb;
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} s;
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always_comb begin
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s = '1;
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s.data[addr_i] = data_i;
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data_o = s.data[addr_o];
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end
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endmodule
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module range_case(
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input logic [2:0] addr_i,
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input logic [7:0] data_i,
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input logic [2:0] addr_o,
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output logic [7:0] data_o
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);
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// (* nowrshmsk = 1 *)
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struct packed {
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logic [7:0] msb;
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logic [0:3][7:0] data;
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logic [7:0] lsb;
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} s;
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always_comb begin
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s = '1;
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s.data[addr_i] = data_i;
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data_o = s.data[addr_o];
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end
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endmodule
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module top;
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logic [7:0] data_shift_mask1;
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range_shift_mask range_shift_mask1(3'd1, 8'h7e, 3'd1, data_shift_mask1);
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logic [7:0] data_shift_mask2;
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range_shift_mask range_shift_mask2(3'd1, 8'h7e, 3'd2, data_shift_mask2);
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logic [7:0] data_shift_mask3;
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range_shift_mask range_shift_mask3(3'd1, 8'h7e, 3'd4, data_shift_mask3);
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always_comb begin
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assert(data_shift_mask1 === 8'h7e);
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assert(data_shift_mask2 === 8'hff);
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assert(data_shift_mask3 === 8'hxx);
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end
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logic [7:0] data_case1;
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range_case range_case1(3'd1, 8'h7e, 3'd1, data_case1);
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logic [7:0] data_case2;
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range_case range_case2(3'd1, 8'h7e, 3'd2, data_case2);
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logic [7:0] data_case3;
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range_case range_case3(3'd1, 8'h7e, 3'd4, data_case3);
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always_comb begin
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assert(data_case1 === 8'h7e);
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assert(data_case2 === 8'hff);
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assert(data_case3 === 8'hxx);
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end
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endmodule
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4
tests/svtypes/struct_dynamic_range.ys
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4
tests/svtypes/struct_dynamic_range.ys
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@ -0,0 +1,4 @@
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read_verilog -sv struct_dynamic_range.sv
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prep -top top
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flatten
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sat -enable_undef -verify -prove-asserts
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