Eddie Hung
8dd93e389e
tests: add testcase for abc9 -dff preserving flop names
2020-05-25 08:43:33 -07:00
Eddie Hung
95dcd7e785
test: add attribute-before-stmt test from @nakengelhardt
2020-05-25 07:36:53 -07:00
Eddie Hung
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
Eddie Hung
29d84339bf
tests: add an generate-else test too
2020-05-25 07:36:53 -07:00
Eddie Hung
589775538c
tests: add #2037 testcase
2020-05-25 07:36:53 -07:00
Eddie Hung
33b03ce904
xaiger: add testcase
2020-05-24 08:48:23 -07:00
Eddie Hung
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Eddie Hung
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
Eddie Hung
e7fd8912f0
tests: attributes before task enable
2020-05-14 16:09:41 -07:00
Eddie Hung
73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
2020-05-14 11:56:22 -07:00
Eddie Hung
13f9d65b6f
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
2020-05-14 10:33:57 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
722540dbf9
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
2020-05-14 10:33:56 -07:00
Eddie Hung
5ad3a85288
abc9: test to use box file instead of auto
2020-05-14 10:33:56 -07:00
Eddie Hung
48052ad813
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
Eddie Hung
8d7b3c06b2
abc9: suppress warnings when no compatible + used flop boxes formed
2020-05-14 10:33:56 -07:00
Eddie Hung
cdd250ef16
xilinx: update abc9_dff tests
2020-05-14 10:33:56 -07:00
Eddie Hung
762b6ad74a
xilinx: remove no-longer-relevant test
2020-05-14 10:33:56 -07:00
Eddie Hung
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
Claire Wolf
140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes
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opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
2020-05-14 18:31:16 +02:00
Claire Wolf
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
Eddie Hung
56a5b1d2da
test: add another testcase as per @nakengelhardt
2020-05-14 08:36:36 -07:00
Eddie Hung
5be4b00a0d
opt_clean: improve warning message
2020-05-14 00:59:38 -07:00
Eddie Hung
aa4a69f89b
opt_clean: add init test
2020-05-14 00:31:08 -07:00
Eddie Hung
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
Peter Crozier
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
Peter Crozier
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
Eddie Hung
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
Eddie Hung
49e64ad492
test: update opt_expr_alu test
2020-05-08 11:12:58 -07:00
Eddie Hung
495acf9815
tests: opt_expr tests that depend on consumex
2020-05-08 11:07:11 -07:00
Peter Crozier
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
Dan Ravensloft
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
Claire Wolf
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
Eddie Hung
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
Zachary Snow
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
Eddie Hung
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
Eddie Hung
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
whitequark
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as logic.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
Eddie Hung
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
Eddie Hung
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
Eddie Hung
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
Claire Wolf
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Eddie Hung
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
Eddie Hung
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
Claire Wolf
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Claire Wolf
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
Eddie Hung
7f203cb019
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
