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Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto

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ast: swap range regardless of range_left >= 0
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Claire Wolf 2020-05-14 18:06:18 +02:00 • committed by GitHub
commit ee0beb481d
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4 changed files with 35 additions and 8 deletions
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tests/verilog/upto.ys Normal file
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@ -0,0 +1,4 @@
read_verilog <<EOT
module top(input [-128:-65] a);
endmodule
EOT