Claire Wolf 140e9a8e06 Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes ... opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically		2020-05-14 18:31:16 +02:00
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aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	intel_alm: direct LUTRAM cell instantiation	2020-05-07 21:03:13 +02:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories
opt	opt_clean: improve warning message	2020-05-14 00:59:38 -07:00
opt_share
proc
realmath
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share
simple	Bugfix in partsel.v signed indices test cases	2020-05-02 11:21:01 +02:00
simple_abc9	Update simple_abc9 tests	2020-02-27 10:17:29 -08:00
smv
sva
svinterfaces
svtypes	support using previously declared types/localparams/params in package	2020-04-07 00:38:15 -04:00
techmap	tests: zinit for new types	2020-04-14 13:08:37 -07:00
tools
unit
various	Merge pull request #2028 from zachjs/master	2020-05-06 12:10:28 -07:00
verilog	techlibs/common: more robustness when *_WIDTH = 0	2020-05-05 08:01:27 -07:00
vloghtb