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Add testcase for #2010

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Eddie Hung 2020-05-01 14:07:33 -07:00
parent 8ee32adac3
commit 7f9ecddb7f
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read_verilog <<EOT
module test (
input signed [1:0] n,
output [3:0] dout
);
assign dout = n + 4'sd 4;
endmodule
EOT
equiv_opt -assert opt -fine