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test: add attribute-before-stmt test from @nakengelhardt

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This commit is contained in:
Eddie Hung 2020-05-14 16:32:14 -07:00
parent 1c117ac023
commit 95dcd7e785
1 changed files with 15 additions and 0 deletions
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15
tests/verilog/bug2037.ys
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@ -41,3 +41,18 @@ module test ();
endmodule
EOT
select -assert-none a:*
design -reset
read_verilog <<EOT
module test ();
localparam y = 1;
reg x = 1'b0;
always @(*) begin
if (y)
(* foo *) x <= 1'b1;
else
(* bar *) x = 1'b0;
end
endmodule
EOT