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techlibs/common: more robustness when *_WIDTH = 0

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This commit is contained in:
Eddie Hung 2020-05-05 08:01:27 -07:00
parent e936ac61ea
commit 004999218f
3 changed files with 30 additions and 8 deletions
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tests/verilog/upto.ys
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@ -2,4 +2,3 @@ read_verilog <<EOT
module top(input [-128:-65] a);
endmodule
EOT
dump