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verilog: allow null gen-if then block

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This commit is contained in:
Zachary Snow 2020-05-04 20:22:16 -04:00
parent 584780d776
commit 8f9bba1bbf
3 changed files with 23 additions and 1 deletions
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13
tests/various/gen_if_null.v Normal file
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@ -0,0 +1,13 @@
module test(x, y, z);
localparam OFF = 0;
generate
if (OFF) ;
else input x;
if (!OFF) input y;
else ;
if (OFF) ;
else ;
if (OFF) ;
input z;
endgenerate
endmodule

4
tests/various/gen_if_null.ys Normal file
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@ -0,0 +1,4 @@
read_verilog gen_if_null.v
select -assert-count 1 test/x
select -assert-count 1 test/y
select -assert-count 1 test/z