2025-09-16 - 2026-03-16
Overview
2 pull requests merged by 1 user
Merged
#24 nlnet-2024-12-324 amendment 1
Merged
#23 switch to use server's new actions org
8 issues closed from 1 user
Closed
#22 NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design
Closed
#21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired.
Closed
#11 NLnet 2024-12-324 Create the fetch and i-cache logic.
Closed
#12 NLnet 2024-12-324 Create the PowerISA decoder
Closed
#10 NLnet 2024-12-324 Create the next-instruction logic
Closed
#13 NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate.
Closed
#4 NLnet 2024-12-324 Write support for board interface descriptions and the code for running the FPGA toolchain (similar to the existing code for running SymbiYosys -- the current formal verification toolchain).
Closed
#6 NLnet 2024-12-324 Add support for the Arty A7 100T since that's what we're using for CI.
4 unresolved conversations
Open
#3
NLnet 2024-12-324 Write the code to do the translation in Fayalite.
Open
#15
NLnet 2024-12-324 memory system: main memory and IO devices
Open
#8
NLnet 2024-12-324 Create a model of the whole rename/execute/retire control system, using procedural implementations of the most complex HDL modules where appropriate.
Open
#5
NLnet 2024-12-324 Add support for the Orange Crab since both Cesar and Jacob have one.