Pulse Contributors Code frequency Recent commits

2025-11-27 - 2026-05-27

Period: 6 months

1 day 3 days 1 week 1 month 3 months 6 months 1 year

Overview

3 active pull requests

8 active issues

3
Merged pull requests 0
Proposed pull requests 8
Closed issues 0
New issues

Excluding merges, 1 author has pushed 8 commits to master and 8 commits to all branches. On master, 3 files have changed and there have been 149 additions and 33 deletions.

3 pull requests merged by 1 user

Merged #26 Replace nlnet-2024-12-324/plan-amendment-1.txt with NLnet's new version since they decided to replace the amendment rather than create an new one 2026-03-23 23:19:00 +00:00

Merged #25 add required skills to nlnet-2024-12-324/progress.md 2026-03-17 05:44:48 +00:00

Merged #24 nlnet-2024-12-324 amendment 1 2026-03-11 01:24:36 +00:00

8 issues closed from 1 user

Closed #8 NLnet 2024-12-324 Create a model of the whole rename/execute/retire control system, using procedural implementations of the most complex HDL modules where appropriate. 2026-05-22 06:58:13 +00:00

Closed #15 NLnet 2024-12-324 memory system: main memory and IO devices 2026-03-26 09:28:28 +00:00

Closed #22 NLnet 2024-12-324 Attempt Proof that our CPU but with zeroed outputs for all eventually-cancelled instructions is equivalent to our real CPU design 2026-03-11 01:27:37 +00:00

Closed #21 NLnet 2024-12-324 Write Rocq and HDL logic for tracking which instructions will eventually be cancelled and which will eventually be retired. 2026-03-11 01:27:17 +00:00

Closed #11 NLnet 2024-12-324 Create the fetch and i-cache logic. 2026-02-22 21:32:50 +00:00

Closed #12 NLnet 2024-12-324 Create the PowerISA decoder 2026-01-29 02:23:38 +00:00

Closed #10 NLnet 2024-12-324 Create the next-instruction logic 2025-12-17 07:55:08 +00:00

Closed #13 NLnet 2024-12-324 Create a model of the instruction fetch/decode control system, using procedural implementations of the most complex HDL modules where appropriate. 2025-12-17 07:55:08 +00:00

10 unresolved conversations

Open #2 NLnet 2024-12-324 Figure out how exactly we should represent HDL in Rocq 2026-05-24 20:39:15 +00:00

Open #20 NLnet 2024-12-324 adding order-violation detection logic 2026-03-17 05:43:04 +00:00

Open #19 NLnet 2024-12-324 adding atomics: lr/sc, atomic fetch-add (or other fetch-op) 2026-03-17 05:42:50 +00:00

Open #18 NLnet 2024-12-324 memory store execution unit 2026-03-17 05:42:31 +00:00

Open #17 NLnet 2024-12-324 memory load execution unit (we'll want to be able to do more than one load at once) 2026-03-17 05:42:14 +00:00

Open #16 NLnet 2024-12-324 d-cache 2026-03-17 05:42:02 +00:00

Open #14 NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL. 2026-03-17 05:41:21 +00:00

Open #9 NLnet 2024-12-324 Translate the procedural model to use actual synthesizeable HDL 2026-03-17 05:39:48 +00:00

Open #5 NLnet 2024-12-324 Add support for the Orange Crab since both Cesar and Jacob have one. 2026-03-17 05:38:33 +00:00

Open #3 NLnet 2024-12-324 Write the code to do the translation in Fayalite. 2026-03-17 05:33:52 +00:00