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NLnet 2024-12-324 Create the fetch and i-cache logic. #11

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opened 2025-08-26 07:03:00 +00:00 by programmerjake · 1 comment
programmerjake commented 2025-08-26 07:03:00 +00:00
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Issue for tracking progress of a subtask of NLnet grant 2024-12-324:
Create the fetch and i-cache logic.

Issue for tracking progress of a subtask of [NLnet grant 2024-12-324](https://git.libre-chip.org/libre-chip/grant-tracking/src/branch/master/nlnet-2024-12-324/progress.md): Create the fetch and i-cache logic. <!-- add additional content here if you like -->
programmerjake added this to the NLnet 2024-12-324 Libre-Chip's First CPU Architecture And Formal Proof of No Spectre bugs project 2025-08-26 07:03:46 +00:00
programmerjake self-assigned this 2026-01-29 16:19:10 +00:00
programmerjake commented 2026-02-22 21:32:50 +00:00
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In libre-chip/cpu#9 I implemented a direct-mapped L1 I-Cache designed to be integrated into the fetch pipeline control logic from #13. The cache has configurable cache line size, cache size, and max number of cache misses that can be in-flight at once. I added a test that checks for proper operation for a particular sequence of operations which covers properly recovering from memory errors, cache misses, and cache hits.

In https://git.libre-chip.org/libre-chip/cpu/pulls/9 I implemented a direct-mapped L1 I-Cache designed to be integrated into the fetch pipeline control logic from https://git.libre-chip.org/libre-chip/grant-tracking/issues/13. The cache has configurable cache line size, cache size, and max number of cache misses that can be in-flight at once. I added a test that checks for proper operation for a particular sequence of operations which covers properly recovering from memory errors, cache misses, and cache hits.
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Reference: libre-chip/grant-tracking#11
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